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Wed, 16 May 2018 17:43:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1526492635; bh=Nflz/VQYbVowpGISYc0Yt1SlTvz7NVyEygeqWFY+Fww=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CjkKInP+bRd0q+IGGsOrajl4EArL7qUjh2tC7ZHd5xnxTBlVQ5two2P1GgHOLSBEs Xl/+297UtP7UffO0qg3nhr3xnEFyQ7tCd7PwkhJlznOa7R6Q4y4bdkb0hqAEZ5WGKD 57AWaWV6S4Ik1EThfPXAxFM+g2lMF5BHS/tggVc0= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 9751660A00 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=rishabhb@codeaurora.org From: Rishabh Bhatnagar To: linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v7 1/2] dt-bindings: Documentation for qcom, llcc Date: Wed, 16 May 2018 10:43:42 -0700 Message-Id: <1526492623-20527-2-git-send-email-rishabhb@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1526492623-20527-1-git-send-email-rishabhb@codeaurora.org> References: <1526492623-20527-1-git-send-email-rishabhb@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180516_104406_247868_61D25F96 X-CRM114-Status: GOOD ( 11.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tsoni@codeaurora.org, robh@kernel.org, ckadabi@codeaurora.org, linux-kernel@vger.kernel.org, evgreen@chromium.org, Rishabh Bhatnagar , linux-arm@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Documentation for last level cache controller device tree bindings, client bindings usage examples. Signed-off-by: Channagoud Kadabi Signed-off-by: Rishabh Bhatnagar Reviewed-by: Rob Herring --- .../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt new file mode 100644 index 0000000..0ebbf0a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt @@ -0,0 +1,26 @@ +== Introduction== + +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC, +that can be shared by multiple clients. Clients here are different cores in the +SOC, the idea is to minimize the local caches at the clients and migrate to +common pool of memory. Cache memory is divided into partitions called slices +which are assigned to clients. Clients can query the slice details, activate +and deactivate them. + +Properties: +- compatible: + Usage: required + Value type: + Definition: must be "qcom,sdm845-llcc" + +- reg: + Usage: required + Value Type: + Definition: Start address and the the size of the register region. + +Example: + + qcom,llcc@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0x1100000 0x250000>; + };