| Message ID | 1526926462-19214-1-git-send-email-will.deacon@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 21/05/18 19:14, Will Deacon wrote: > Now that we're seeing CPUs shipping with LSE atomics, default them to > 'on' in Kconfig. CPUs without the instructions will continue to use > LDXR/STXR-based sequences, but they will be placed out-of-line by the > compiler. > > Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> M.
On Mon, May 21, 2018 at 07:14:22PM +0100, Will Deacon wrote: > Now that we're seeing CPUs shipping with LSE atomics, default them to > 'on' in Kconfig. CPUs without the instructions will continue to use > LDXR/STXR-based sequences, but they will be placed out-of-line by the > compiler. > > Signed-off-by: Will Deacon <will.deacon@arm.com> I've been fuzzing v4.17-rc3 with this enabled, and haven't hit anything new that appears to be caused by the atomics. FWIW: Acked-by: Mark Rutland <mark.rutland@arm.com> Mark. > --- > arch/arm64/Kconfig | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 4d98774cf3c7..3aed13626fd7 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1051,6 +1051,7 @@ config ARM64_PAN > > config ARM64_LSE_ATOMICS > bool "Atomic instructions" > + default y > help > As part of the Large System Extensions, ARMv8.1 introduces new > atomic instructions that are designed specifically to scale in > @@ -1059,7 +1060,8 @@ config ARM64_LSE_ATOMICS > Say Y here to make use of these instructions for the in-kernel > atomic routines. This incurs a small overhead on CPUs that do > not support these instructions and requires the kernel to be > - built with binutils >= 2.25. > + built with binutils >= 2.25 in order for the new instructions > + to be used. > > config ARM64_VHE > bool "Enable support for Virtualization Host Extensions (VHE)" > -- > 2.1.4 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Mon, May 21, 2018 at 07:14:22PM +0100, Will Deacon wrote: > Now that we're seeing CPUs shipping with LSE atomics, default them to > 'on' in Kconfig. CPUs without the instructions will continue to use > LDXR/STXR-based sequences, but they will be placed out-of-line by the > compiler. > > Signed-off-by: Will Deacon <will.deacon@arm.com> Queued for 4.18. Thanks.
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 4d98774cf3c7..3aed13626fd7 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1051,6 +1051,7 @@ config ARM64_PAN config ARM64_LSE_ATOMICS bool "Atomic instructions" + default y help As part of the Large System Extensions, ARMv8.1 introduces new atomic instructions that are designed specifically to scale in @@ -1059,7 +1060,8 @@ config ARM64_LSE_ATOMICS Say Y here to make use of these instructions for the in-kernel atomic routines. This incurs a small overhead on CPUs that do not support these instructions and requires the kernel to be - built with binutils >= 2.25. + built with binutils >= 2.25 in order for the new instructions + to be used. config ARM64_VHE bool "Enable support for Virtualization Host Extensions (VHE)"
Now that we're seeing CPUs shipping with LSE atomics, default them to 'on' in Kconfig. CPUs without the instructions will continue to use LDXR/STXR-based sequences, but they will be placed out-of-line by the compiler. Signed-off-by: Will Deacon <will.deacon@arm.com> --- arch/arm64/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)