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Wed, 23 May 2018 12:53:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527080013; bh=RLeKw+yUITeByQPqgWNTo/ziCo4iAaputZTsrtN9p1M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UTdiZELJAgTYVcl3mAcyf4OMNGhoqsGyoMg9I8t5uheZ0pVJQAuwO67W0Gis7gWvA iOoUlxfCAxBH95CGRRIKF7+Gbiue/Tm785Vk37Hsj0cqZ75Q0DnRtVppMymYk1TyAR yBWtXEVjzTN3+k6IpUNaAKRA/jeVfviTmsX84TZY= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org ACEC460F61 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=ilialin@codeaurora.org From: Ilia Lin To: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, david.brown@linaro.org, will.deacon@arm.com Subject: [PATCH v11 7/8] clk: qcom: cpu-8996: Add support to switch below 600Mhz Date: Wed, 23 May 2018 15:53:00 +0300 Message-Id: <1527079981-11179-8-git-send-email-ilialin@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org> References: <1527079981-11179-1-git-send-email-ilialin@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180523_055342_769556_F7D6DC4B X-CRM114-Status: GOOD ( 15.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Rajendra Nayak , linux-arm-msm@vger.kernel.org, ilialin@codeaurora.org, linux-kernel@vger.kernel.org, vireshk@kernel.org, linux-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The CPU clock controller's primary PLL operates on a single VCO range, between 600MHz and 3GHz. However the CPUs do support OPPs with frequencies between 300MHz and 600MHz. In order to support running the CPUs at those frequencies we end up having to lock the PLL at twice the rate and drive the CPU clk via the PLL/2 output and SMUX. So for frequencies above 600MHz we follow the following path Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk and for frequencies between 300MHz and 600MHz we follow Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk Signed-off-by: Rajendra Nayak Signed-off-by: Ilia Lin --- drivers/clk/qcom/clk-cpu-8996.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c index 620fdc2..ff5c0a5 100644 --- a/drivers/clk/qcom/clk-cpu-8996.c +++ b/drivers/clk/qcom/clk-cpu-8996.c @@ -68,6 +68,8 @@ enum _pmux_input { NUM_OF_PMUX_INPUTS }; +#define DIV_2_THRESHOLD 600000000 + static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = { [PLL_OFF_L_VAL] = 0x04, [PLL_OFF_ALPHA_VAL] = 0x08, @@ -95,10 +97,11 @@ enum _pmux_input { static const struct alpha_pll_config hfpll_config = { .l = 60, - .config_ctl_val = 0x200d4828, + .config_ctl_val = 0x200d4aa8, .config_ctl_hi_val = 0x006, .pre_div_mask = BIT(12), .post_div_mask = 0x3 << 8, + .post_div_val = 0x1 << 8, .main_output_mask = BIT(0), .early_output_mask = BIT(3), }; @@ -140,7 +143,7 @@ enum _pmux_input { .vco_mask = 0x3 << 20, .config_ctl_val = 0x4001051b, .post_div_mask = 0x3 << 8, - .post_div_val = 0x1, + .post_div_val = 0x1 << 8, .main_output_mask = BIT(0), .early_output_mask = BIT(3), }; @@ -181,6 +184,7 @@ struct clk_cpu_8996_mux { u8 width; struct notifier_block nb; struct clk_hw *pll; + struct clk_hw *pll_div_2; struct clk_regmap clkr; }; @@ -226,6 +230,13 @@ static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index) struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw); struct clk_hw *parent = cpuclk->pll; + if (cpuclk->pll_div_2 && req->rate < DIV_2_THRESHOLD) { + if (req->rate < (DIV_2_THRESHOLD / 2)) + return -EINVAL; + + parent = cpuclk->pll_div_2; + } + req->best_parent_rate = clk_hw_round_rate(parent, req->rate); req->best_parent_hw = parent; @@ -237,13 +248,19 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, { int ret; struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_nb(nb); + struct clk_notifier_data *cnd = data; switch (event) { case PRE_RATE_CHANGE: ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, ALT_INDEX); break; case POST_RATE_CHANGE: - ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, PLL_INDEX); + if (cnd->new_rate < DIV_2_THRESHOLD) + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + DIV_2_INDEX); + else + ret = clk_cpu_8996_mux_set_parent(&cpuclk->clkr.hw, + PLL_INDEX); break; default: ret = 0; @@ -295,6 +312,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &pwrcl_pll.clkr.hw, + .pll_div_2 = &pwrcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "pwrcl_pmux", @@ -315,6 +333,7 @@ int cpu_clk_notifier_cb(struct notifier_block *nb, unsigned long event, .shift = 0, .width = 2, .pll = &perfcl_pll.clkr.hw, + .pll_div_2 = &perfcl_smux.clkr.hw, .nb.notifier_call = cpu_clk_notifier_cb, .clkr.hw.init = &(struct clk_init_data) { .name = "perfcl_pmux",