From patchwork Thu May 31 08:15:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honghui Zhang X-Patchwork-Id: 10440521 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C0AF26035E for ; Thu, 31 May 2018 08:16:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B21BE29152 for ; Thu, 31 May 2018 08:16:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A40BE2916B; Thu, 31 May 2018 08:16:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, MAILING_LIST_MULTI, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9388C29152 for ; Thu, 31 May 2018 08:16:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To :From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=DMxn5q7+MEXXJ5qI4dbp6DrVL7BBLqjcLBjZ3atFSFE=; b=Fi2NCfWo9czfxm fxNCaGlS9xI7hK2luiLuyNOPoVghUQLhEJCjVL1fGvwX+QD+AGNxPQvkQUF4+AmaAUoZtcY2dz7Dx f396c3krtzJpEoDnEVNsgG82zGsxjCHP/SjdC8qIuaeaw7t777oZh/zueUiE4XCufn9mg3kf5y3ZZ ZZ5mh0c9uIVFQEuImyaoGljKp16zr97KAPoOQY5/casU18sb77dmhMwq5U6pdGP3u9zSlhgyqOdfe JcVFsJPyt0nh1NGHlociYjW6I6mG7MbR5EqF3HorI46zMyTI3/DuQdE0tlJYATgkRvXaJ65COeD55 PLVM+trSlacAGQtr/TlA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fOIkq-0001AM-7b; Thu, 31 May 2018 08:16:16 +0000 Received: from [210.61.82.184] (helo=mailgw02.mediatek.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fOIkm-00019a-Nj; Thu, 31 May 2018 08:16:14 +0000 X-UUID: 683e0f467981477fb38c721d9abd94c9-20180531 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1039495158; Thu, 31 May 2018 16:15:57 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Thu, 31 May 2018 16:15:48 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Thu, 31 May 2018 16:15:47 +0800 From: To: , , , , , , , , , , , Subject: [PATCH v2] PCI: mediatek: Add system pm support for MT2712 Date: Thu, 31 May 2018 16:15:45 +0800 Message-ID: <1527754545-32378-1-git-send-email-honghui.zhang@mediatek.com> X-Mailer: git-send-email 2.6.4 MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180531_011612_917281_50E0AD44 X-CRM114-Status: GOOD ( 13.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, hongkun.cao@mediatek.com, sean.wang@mediatek.com, xinping.qian@mediatek.com, honghui.zhang@mediatek.com, yt.shen@mediatek.com, yong.wu@mediatek.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Honghui Zhang The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all the internal control register will be reset after system resume. The PCIe link should be re-established and the related control register values should be re-set after system resume. Signed-off-by: Honghui Zhang CC: Ryder Lee --- drivers/pci/host/pcie-mediatek.c | 61 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c index dabf1086..6bf7f5a 100644 --- a/drivers/pci/host/pcie-mediatek.c +++ b/drivers/pci/host/pcie-mediatek.c @@ -132,12 +132,14 @@ struct mtk_pcie_port; /** * struct mtk_pcie_soc - differentiate between host generations * @need_fix_class_id: whether this host's class ID needed to be fixed or not + * @pm_support: whether the host's MTCMOS will be off when suspend * @ops: pointer to configuration access functions * @startup: pointer to controller setting functions * @setup_irq: pointer to initialize IRQ functions */ struct mtk_pcie_soc { bool need_fix_class_id; + bool pm_support; struct pci_ops *ops; int (*startup)(struct mtk_pcie_port *port); int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node); @@ -1179,12 +1181,70 @@ static int mtk_pcie_probe(struct platform_device *pdev) return err; } +#ifdef CONFIG_PM_SLEEP +static int mtk_pcie_suspend_noirq(struct device *dev) +{ + struct mtk_pcie *pcie = dev_get_drvdata(dev); + const struct mtk_pcie_soc *soc = pcie->soc; + struct mtk_pcie_port *port; + + if (!soc->pm_support) + return 0; + + list_for_each_entry(port, &pcie->ports, list) { + clk_disable_unprepare(port->ahb_ck); + clk_disable_unprepare(port->sys_ck); + phy_power_off(port->phy); + } + + return 0; +} + +static int mtk_pcie_resume_noirq(struct device *dev) +{ + struct mtk_pcie *pcie = dev_get_drvdata(dev); + const struct mtk_pcie_soc *soc = pcie->soc; + struct mtk_pcie_port *port; + int ret; + + soc = pcie->soc; + if (!soc->pm_support) + return 0; + + list_for_each_entry(port, &pcie->ports, list) { + phy_power_on(port->phy); + clk_prepare_enable(port->sys_ck); + clk_prepare_enable(port->ahb_ck); + + ret = soc->startup(port); + if (ret) { + dev_err(dev, "Port%d link down\n", port->slot); + phy_power_off(port->phy); + clk_disable_unprepare(port->sys_ck); + clk_disable_unprepare(port->ahb_ck); + return ret; + } + + if (IS_ENABLED(CONFIG_PCI_MSI)) + mtk_pcie_enable_msi(port); + } + + return 0; +} +#endif + +const struct dev_pm_ops mtk_pcie_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, + mtk_pcie_resume_noirq) +}; + static const struct mtk_pcie_soc mtk_pcie_soc_v1 = { .ops = &mtk_pcie_ops, .startup = mtk_pcie_startup_port, }; static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = { + .pm_support = true, .ops = &mtk_pcie_ops_v2, .startup = mtk_pcie_startup_port_v2, .setup_irq = mtk_pcie_setup_irq, @@ -1211,6 +1271,7 @@ static struct platform_driver mtk_pcie_driver = { .name = "mtk-pcie", .of_match_table = mtk_pcie_ids, .suppress_bind_attrs = true, + .pm = &mtk_pcie_pm_ops, }, }; builtin_platform_driver(mtk_pcie_driver);