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Thu, 07 Jun 2018 05:12:07 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1fQtlq-0001FQ-DU; Thu, 07 Jun 2018 05:12:02 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id w57CBx2N001684; Thu, 7 Jun 2018 05:11:59 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1fQtlm-0001Ev-Tb; Thu, 07 Jun 2018 05:11:59 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 1E4F21214C7; Thu, 7 Jun 2018 17:41:58 +0530 (IST) From: Manish Narani To: , , , , , , , , , , , , Subject: [RFC PATCH 2/3] dt: bindings: Add SD tap value properties details Date: Thu, 7 Jun 2018 17:41:39 +0530 Message-ID: <1528373500-24663-2-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1528373500-24663-1-git-send-email-manish.narani@xilinx.com> References: <1528373500-24663-1-git-send-email-manish.narani@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY1PR0201MB0871 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20180607_051227_475025_FB56426E X-CRM114-Status: UNSURE ( 9.83 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Manish Narani Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds details of SD tap value properties in device tree. Signed-off-by: Manish Narani --- .../devicetree/bindings/mmc/arasan,sdhci.txt | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) -- 2.7.4 This email and any attachments are intended for the sole use of the named recipient(s) and contain(s) confidential information that may be proprietary, privileged or copyrighted under applicable law. If you are not the intended recipient, do not read, copy, or forward this email message or any attachments. Delete this email message and any attachments immediately. diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index 60481bf..0e08877 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -15,6 +15,8 @@ Required Properties: - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY For this device it is strongly suggested to include arasan,soc-ctl-syscon. + - "xlnx,zynqmp-8.9a": Xilinx ZynqMP Arasan SDHCI 8.9a PHY + For this device it is strongly suggested to include arasan,soc-ctl-syscon. - reg: From mmc bindings: Register location and length. - clocks: From clock bindings: Handles to clock inputs. - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" @@ -26,6 +28,30 @@ Required Properties for "arasan,sdhci-5.1": - phys: From PHY bindings: Phandle for the Generic PHY for arasan. - phy-names: MUST be "phy_arasan". +Required Properties for "xlnx,zynqmp-8.9a": + - xlnx,mio_bank: The value will be 0/1/2 depending on MIO bank selection. + - xlnx,device_id: Unique Id of the device, value will be 0/1. + - xlnx,itap_delay_sd_hsd: Input Tap Delay for SD HS. + - xlnx,itap_delay_sdr25: Input Tap Delay for SDR25. + - xlnx,itap_delay_sdr50: Input Tap Delay for SDR50. + - xlnx,itap_delay_sdr104_b0: Input Tap Delay for SDR104. + - xlnx,itap_delay_sdr104_b2: Input Tap Delay for SDR104. + - xlnx,itap_delay_sd_ddr50: Input Tap Delay for SD DDR50. + - xlnx,itap_delay_mmc_hsd: Input Tap Delay for MMC HS. + - xlnx,itap_delay_mmc_ddr50: Input Tap Delay for MMC DDR50. + - xlnx,itap_delay_mmc_hs200_b0: Input Tap Delay for MMC HS200. + - xlnx,itap_delay_mmc_hs200_b2: Input Tap Delay for MMC HS200. + - xlnx,otap_delay_sd_hsd: Output Tap Delay for SD HS. + - xlnx,otap_delay_sdr25: Output Tap Delay for SDR25. + - xlnx,otap_delay_sdr50: Output Tap Delay for SDR50. + - xlnx,otap_delay_sdr104_b0: Output Tap Delay for SDR104. + - xlnx,otap_delay_sdr104_b2: Output Tap Delay for SDR104. + - xlnx,otap_delay_sd_ddr50: Output Tap Delay for DDR50. + - xlnx,otap_delay_mmc_hsd: Output Tap Delay for MMC HS. + - xlnx,otap_delay_mmc_ddr50: Output Tap Delay for MMC DDR50. + - xlnx,otap_delay_mmc_hs200_b0: Output Tap Delay for MMC HS200. + - xlnx,otap_delay_mmc_hs200_b2: Output Tap Delay for MMC HS200. + Optional Properties: - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) used to access core corecfg registers. Offsets of registers in this