From patchwork Tue Oct 2 11:12:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 10623383 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id AA6E01515 for ; Tue, 2 Oct 2018 11:14:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9246428749 for ; Tue, 2 Oct 2018 11:14:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 85A62287CD; Tue, 2 Oct 2018 11:14:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A4D6728749 for ; Tue, 2 Oct 2018 11:14:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=8B9678TbWK1jGn/5EEh8+XzSn1mYf/Xuf+0aTWsgSI8=; b=aQ3AR7SF0bjNOkvQGobC4x74vW v75pbD3DOhki4epMhfYa1OwO48v94SPApX83paBvvxHo4OVk0r5afdDVnKxJUyXi/L0eSSS4g73tb Get8jQcCJC+iT6si/gbtFGu/fjcSUW0dAYUdulbMqOcIz3GV5C4Tsiua9M4SNKHd9qsTOOavzrTeA uEwZzy5Vu8NkfWGj8uKy3Ip2GVMzp1bqvDAIWY1Y35lAacfSkkkYS5OzYzUzm7tcnEaisa4S64n09 3xmQy1OCYOru/BqkBmPDeMS5U7X8DCeBqIqvnQF/N52BIjMQ/L7hesxI4JUcMn625b5LC+vEuSX00 XxwHOr+A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g7IdP-0004Xx-3y; Tue, 02 Oct 2018 11:14:35 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1g7IbQ-0003g2-Sn for linux-arm-kernel@lists.infradead.org; Tue, 02 Oct 2018 11:12:42 +0000 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 02 Oct 2018 20:12:23 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id CCA196006C; Tue, 2 Oct 2018 20:12:23 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 2 Oct 2018 20:12:23 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 1D28B1A03A2; Tue, 2 Oct 2018 20:12:23 +0900 (JST) From: Kunihiko Hayashi To: Masahiro Yamada , linux-arm-kernel@lists.infradead.org Subject: [PATCH 3/4] arm64: dts: uniphier: Add USB3 controller nodes Date: Tue, 2 Oct 2018 20:12:01 +0900 Message-Id: <1538478722-20351-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1538478722-20351-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1538478722-20351-1-git-send-email-hayashi.kunihiko@socionext.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181002_041233_449513_2EA24B38 X-CRM114-Status: GOOD ( 14.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Masami Hiramatsu , Kunihiko Hayashi , Jassi Brar , Rob Herring MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add USB3 controller nodes including usb-core, resets, regulator, ss-phy and hs-phy. This supports for LD20, PXs3 and the boards. This includes additional efuse nodes for obtaining PHY trimming values. Signed-off-by: Kunihiko Hayashi --- .../boot/dts/socionext/uniphier-ld20-global.dts | 4 + .../arm64/boot/dts/socionext/uniphier-ld20-ref.dts | 4 + arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 194 +++++++++++++++++ .../arm64/boot/dts/socionext/uniphier-pxs3-ref.dts | 8 + arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 240 +++++++++++++++++++++ 5 files changed, 450 insertions(+) diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts index 1a5e7c2..d7ae28a 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-global.dts @@ -148,3 +148,7 @@ &nand { status = "okay"; }; + +&usb { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts index 440c2e6..406244a 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts @@ -75,3 +75,7 @@ drive-strength = <9>; }; }; + +&usb { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index caf1126..dcf6178 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -553,6 +553,50 @@ efuse@200 { compatible = "socionext,uniphier-efuse"; reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* USB cells */ + usb_rterm0: trim@54,4 { + reg = <0x54 1>; + bits = <4 2>; + }; + usb_rterm1: trim@55,4 { + reg = <0x55 1>; + bits = <4 2>; + }; + usb_rterm2: trim@58,4 { + reg = <0x58 1>; + bits = <4 2>; + }; + usb_rterm3: trim@59,4 { + reg = <0x59 1>; + bits = <4 2>; + }; + usb_sel_t0: trim@54,0 { + reg = <0x54 1>; + bits = <0 4>; + }; + usb_sel_t1: trim@55,0 { + reg = <0x55 1>; + bits = <0 4>; + }; + usb_sel_t2: trim@58,0 { + reg = <0x58 1>; + bits = <0 4>; + }; + usb_sel_t3: trim@59,0 { + reg = <0x59 1>; + bits = <0 4>; + }; + usb_hs_i0: trim@56,0 { + reg = <0x56 1>; + bits = <0 4>; + }; + usb_hs_i2: trim@5a,0 { + reg = <0x5a 1>; + bits = <0 4>; + }; }; }; @@ -620,6 +664,156 @@ }; }; + usb: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host"; + interrupts = <0 134 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, + <&pinctrl_usb2>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; + resets = <&usb_rst 15>; + phys = <&usb_hsphy0>, <&usb_hsphy1>, + <&usb_hsphy2>, <&usb_hsphy3>, + <&usb_ssphy0>, <&usb_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-ld20-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb_rst: reset@0 { + compatible = "socionext,uniphier-ld20-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus0: regulator@100 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus1: regulator@110 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus2: regulator@120 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x120 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_vbus3: regulator@130 { + compatible = "socionext,uniphier-ld20-usb3-regulator"; + reg = <0x130 0x10>; + clock-names = "link"; + clocks = <&sys_clk 14>; + reset-names = "link"; + resets = <&sys_rst 14>; + }; + + usb_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, + <&usb_hs_i0>; + }; + + usb_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 16>; + vbus-supply = <&usb_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, + <&usb_hs_i0>; + }; + + usb_hsphy2: hs-phy@220 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x220 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb_vbus2>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, + <&usb_hs_i2>; + }; + + usb_hsphy3: hs-phy@230 { + compatible = "socionext,uniphier-ld20-usb3-hsphy"; + reg = <0x230 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 17>; + vbus-supply = <&usb_vbus3>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, + <&usb_hs_i2>; + }; + + usb_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 18>; + vbus-supply = <&usb_vbus0>; + }; + + usb_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-ld20-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 14>, <&sys_clk 19>; + reset-names = "link", "phy"; + resets = <&sys_rst 14>, <&sys_rst 19>; + vbus-supply = <&usb_vbus1>; + }; + }; + nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled"; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts index c1bb607..b00db39 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts @@ -100,3 +100,11 @@ &nand { status = "okay"; }; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 2a4cf42..f688bd7 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -366,6 +366,50 @@ efuse@200 { compatible = "socionext,uniphier-efuse"; reg = <0x200 0x68>; + #address-cells = <1>; + #size-cells = <1>; + + /* USB cells */ + usb_rterm0: trim@54,4 { + reg = <0x54 1>; + bits = <4 2>; + }; + usb_rterm1: trim@55,4 { + reg = <0x55 1>; + bits = <4 2>; + }; + usb_rterm2: trim@58,4 { + reg = <0x58 1>; + bits = <4 2>; + }; + usb_rterm3: trim@59,4 { + reg = <0x59 1>; + bits = <4 2>; + }; + usb_sel_t0: trim@54,0 { + reg = <0x54 1>; + bits = <0 4>; + }; + usb_sel_t1: trim@55,0 { + reg = <0x55 1>; + bits = <0 4>; + }; + usb_sel_t2: trim@58,0 { + reg = <0x58 1>; + bits = <0 4>; + }; + usb_sel_t3: trim@59,0 { + reg = <0x59 1>; + bits = <0 4>; + }; + usb_hs_i0: trim@56,0 { + reg = <0x56 1>; + bits = <0 4>; + }; + usb_hs_i2: trim@5a,0 { + reg = <0x5a 1>; + bits = <0 4>; + }; }; }; @@ -447,6 +491,202 @@ }; }; + usb0: usb@65a00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65a00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 134 4>, <0 135 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; + resets = <&usb0_rst 15>; + phys = <&usb0_hsphy0>, <&usb0_hsphy1>, + <&usb0_ssphy0>, <&usb0_ssphy1>; + dr_mode = "host"; + }; + + usb-glue@65b00000 { + compatible = "socionext,uniphier-pxs3-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65b00000 0x400>; + + usb0_rst: reset@0 { + compatible = "socionext,uniphier-pxs3-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 12>; + reset-names = "link"; + resets = <&sys_rst 12>; + }; + + usb0_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, + <&usb_hs_i0>; + }; + + usb0_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 16>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 16>; + vbus-supply = <&usb0_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, + <&usb_hs_i0>; + }; + + usb0_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 17>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 17>; + vbus-supply = <&usb0_vbus0>; + }; + + usb0_ssphy1: ss-phy@310 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x310 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 12>, <&sys_clk 18>; + reset-names = "link", "phy"; + resets = <&sys_rst 12>, <&sys_rst 18>; + vbus-supply = <&usb0_vbus1>; + }; + }; + + usb1: usb@65c00000 { + compatible = "socionext,uniphier-dwc3", "snps,dwc3"; + status = "disabled"; + reg = <0x65c00000 0xcd00>; + interrupt-names = "host", "peripheral"; + interrupts = <0 137 4>, <0 138 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; + clock-names = "ref", "bus_early", "suspend"; + clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; + resets = <&usb1_rst 15>; + phys = <&usb1_hsphy0>, <&usb1_hsphy1>, + <&usb1_ssphy0>; + dr_mode = "host"; + }; + + usb-glue@65d00000 { + compatible = "socionext,uniphier-pxs3-dwc3-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65d00000 0x400>; + + usb1_rst: reset@0 { + compatible = "socionext,uniphier-pxs3-usb3-reset"; + reg = <0x0 0x4>; + #reset-cells = <1>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_vbus0: regulator@100 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x100 0x10>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_vbus1: regulator@110 { + compatible = "socionext,uniphier-pxs3-usb3-regulator"; + reg = <0x110 0x10>; + clock-names = "link"; + clocks = <&sys_clk 13>; + reset-names = "link"; + resets = <&sys_rst 13>; + }; + + usb1_hsphy0: hs-phy@200 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x200 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 20>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus0>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, + <&usb_hs_i2>; + }; + + usb1_hsphy1: hs-phy@210 { + compatible = "socionext,uniphier-pxs3-usb3-hsphy"; + reg = <0x210 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 20>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 20>; + vbus-supply = <&usb1_vbus1>; + nvmem-cell-names = "rterm", "sel_t", "hs_i"; + nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, + <&usb_hs_i2>; + }; + + usb1_ssphy0: ss-phy@300 { + compatible = "socionext,uniphier-pxs3-usb3-ssphy"; + reg = <0x300 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy", "phy-ext"; + clocks = <&sys_clk 13>, <&sys_clk 21>, + <&sys_clk 14>; + reset-names = "link", "phy"; + resets = <&sys_rst 13>, <&sys_rst 21>; + vbus-supply = <&usb1_vbus0>; + }; + }; + nand: nand@68000000 { compatible = "socionext,uniphier-denali-nand-v5b"; status = "disabled";