From patchwork Thu Oct 18 05:07:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jianxin Pan X-Patchwork-Id: 10646715 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C7A1213B0 for ; Thu, 18 Oct 2018 05:08:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B4155287E8 for ; Thu, 18 Oct 2018 05:08:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A29BC2880B; Thu, 18 Oct 2018 05:08:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 22F25287E8 for ; Thu, 18 Oct 2018 05:08:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ocNjlsfll6nT/r+I0tteqbTLKynOR5j5maQEcB5bgC0=; b=Lr3hH2CFrKB4YW Io6DthU/Hxx1Uxgmk+bKRDl7jQ07+FGAuZfE/Lypf1s4y3E0eIdJz5KXREuK4ZEadJ4LvMsqIyZrR Er52ecF0lpfgNLFNKs2ZPXzkyA8oEBkeap6bu2iKJyssQlHtV6uDazD53gUdd3ZSTgURycmHTYVOd 5vKcALwkfVPWz4KiRvb2yXvovv1RfvhV2IWNG5Luc5oH0kKDlH9+MY+tld7Rcxx27uBTzvrGUNW44 ixq8nS+X2NbGgVpMhwn4hwlJZhUwQ7J48LQhp1Md92VMzIf5I2/vU61BUZum8rbmKfoMExMqlHT3K CSWtvdzbrRFMK1V+qT7Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gD0Y7-0004FB-KV; Thu, 18 Oct 2018 05:08:43 +0000 Received: from mail-sh2.amlogic.com ([58.32.228.45]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gD0Xc-0003wl-GY; Thu, 18 Oct 2018 05:08:27 +0000 Received: from localhost.localdomain (10.18.11.217) by mail-sh2.amlogic.com (10.18.11.6) with Microsoft SMTP Server id 15.0.1320.4; Thu, 18 Oct 2018 13:07:27 +0800 From: Jianxin Pan To: Jerome Brunet , Neil Armstrong Subject: [PATCH v5 1/3] clk: meson: add emmc sub clock phase delay driver Date: Thu, 18 Oct 2018 13:07:23 +0800 Message-ID: <1539839245-13793-2-git-send-email-jianxin.pan@amlogic.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> References: <1539839245-13793-1-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.18.11.217] X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181017_220812_576416_3318FB7E X-CRM114-Status: GOOD ( 13.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Hanjie Lin , Victor Wan , Jianxin Pan , devicetree@vger.kernel.org, Stephen Boyd , Kevin Hilman , Michael Turquette , Yixun Lan , linux-kernel@vger.kernel.org, Boris Brezillon , Liang Yang , Jian Hu , Miquel Raynal , Carlo Caione , linux-amlogic@lists.infradead.org, Martin Blumenstingl , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Qiufang Dai Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Yixun Lan Export the emmc sub clock phase delay ops which will be used by the emmc sub clock driver itself. Signed-off-by: Yixun Lan Signed-off-by: Jianxin Pan --- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/clk-phase-delay.c | 79 +++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 13 ++++++ 3 files changed, 93 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/clk-phase-delay.c diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index 72ec8c4..39ce566 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -2,7 +2,7 @@ # Makefile for Meson specific clk # -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o clk-phase-delay.o obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o diff --git a/drivers/clk/meson/clk-phase-delay.c b/drivers/clk/meson/clk-phase-delay.c new file mode 100644 index 0000000..b9573a7 --- /dev/null +++ b/drivers/clk/meson/clk-phase-delay.c @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Amlogic Meson MMC Sub Clock Controller Driver + * + * Copyright (c) 2017 Baylibre SAS. + * Author: Jerome Brunet + * + * Copyright (c) 2018 Amlogic, inc. + * Author: Yixun Lan + */ + +#include +#include "clkc.h" + +static int meson_clk_phase_delay_get_phase(struct clk_hw *hw) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph = + meson_clk_get_phase_delay_data(clk); + unsigned long period_ps, p, d; + int degrees; + u32 val; + + regmap_read(clk->map, ph->phase.reg_off, &val); + p = PARM_GET(ph->phase.width, ph->phase.shift, val); + degrees = p * 360 / (1 << (ph->phase.width)); + + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_hw_get_rate(hw)); + + d = PARM_GET(ph->delay.width, ph->delay.shift, val); + degrees += d * ph->delay_step_ps * 360 / period_ps; + degrees %= 360; + + return degrees; +} + +static void meson_clk_apply_phase_delay(struct clk_regmap *clk, + unsigned int phase, + unsigned int delay) +{ + struct meson_clk_phase_delay_data *ph = clk->data; + u32 val; + + regmap_read(clk->map, ph->delay.reg_off, &val); + val = PARM_SET(ph->phase.width, ph->phase.shift, val, phase); + val = PARM_SET(ph->delay.width, ph->delay.shift, val, delay); + regmap_write(clk->map, ph->delay.reg_off, val); +} + +static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees) +{ + struct clk_regmap *clk = to_clk_regmap(hw); + struct meson_clk_phase_delay_data *ph = + meson_clk_get_phase_delay_data(clk); + unsigned long period_ps, d = 0, r; + u64 p; + + p = degrees % 360; + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000, + clk_hw_get_rate(hw)); + + /* First compute the phase index (p), the remainder (r) is the + * part we'll try to acheive using the delays (d). + */ + r = do_div(p, 360 / (1 << (ph->phase.width))); + d = DIV_ROUND_CLOSEST(r * period_ps, + 360 * ph->delay_step_ps); + d = min(d, PMASK(ph->delay.width)); + + meson_clk_apply_phase_delay(clk, p, d); + return 0; +} + +const struct clk_ops meson_clk_phase_delay_ops = { + .get_phase = meson_clk_phase_delay_get_phase, + .set_phase = meson_clk_phase_delay_set_phase, +}; +EXPORT_SYMBOL_GPL(meson_clk_phase_delay_ops); diff --git a/drivers/clk/meson/clkc.h b/drivers/clk/meson/clkc.h index 6b96d55..3309d78 100644 --- a/drivers/clk/meson/clkc.h +++ b/drivers/clk/meson/clkc.h @@ -105,6 +105,18 @@ struct clk_regmap _name = { \ }, \ }; +struct meson_clk_phase_delay_data { + struct parm phase; + struct parm delay; + unsigned int delay_step_ps; +}; + +static inline struct meson_clk_phase_delay_data * +meson_clk_get_phase_delay_data(struct clk_regmap *clk) +{ + return (struct meson_clk_phase_delay_data *)clk->data; +} + /* clk_ops */ extern const struct clk_ops meson_clk_pll_ro_ops; extern const struct clk_ops meson_clk_pll_ops; @@ -112,5 +124,6 @@ struct clk_regmap _name = { \ extern const struct clk_ops meson_clk_mpll_ro_ops; extern const struct clk_ops meson_clk_mpll_ops; extern const struct clk_ops meson_clk_phase_ops; +extern const struct clk_ops meson_clk_phase_delay_ops; #endif /* __CLKC_H */