From patchwork Fri Oct 26 07:51:19 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yang Yingliang X-Patchwork-Id: 10657039 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id DDF07109C for ; Fri, 26 Oct 2018 07:53:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CF9E227EED for ; Fri, 26 Oct 2018 07:53:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C1E3927FB7; Fri, 26 Oct 2018 07:53:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 3721227EED for ; Fri, 26 Oct 2018 07:53:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jOkRnAI3P2iI1jXawRjHrmshCljTLlo4gyTTxpnEz6o=; b=D4JT+eR088bW6a z+zU7B5APnd564XKLuFXfYxa1eRG5NNImF89XZeo5VIn0IeBjk3KlGBhSFre9Hk07iXZlS3jGbjLQ HZKbGTVBpCXoPnzIIAuad7E59/T3BvFvh/GyRBk3A42gPVT/dpY+9RsmYKKD+0vkJzY19NMstRtqa qLQREvYOVs1QL/hxPRqAK8eW5l2En4Pw3QUrTNCUuy+VHwzMgqBXC3Xs5rUpLQiy7ON0kufaDy6oj xgPHgGeOxp5DF0I60zb94us/ITzt+Vz1iyGkVyFjh+D4EjxquvL7w+uO3dN3Kg8DE13Kwk+pdomF5 /o2wiD+QmL7hbqYsHfRg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gFwve-0001LK-1d; Fri, 26 Oct 2018 07:53:10 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gFwuN-0000ip-O5 for linux-arm-kernel@lists.infradead.org; Fri, 26 Oct 2018 07:51:55 +0000 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id D9C85AE3095BF; Fri, 26 Oct 2018 15:51:34 +0800 (CST) Received: from localhost (10.177.19.219) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.408.0; Fri, 26 Oct 2018 15:51:26 +0800 From: Yang Yingliang To: , Subject: [PATCH v2 3/4] irqchip/mbigen: add support for a MBIGEN generating SPIs Date: Fri, 26 Oct 2018 15:51:19 +0800 Message-ID: <1540540280-26612-4-git-send-email-yangyingliang@huawei.com> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> References: <1540540280-26612-1-git-send-email-yangyingliang@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.177.19.219] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181026_005151_956254_DC153853 X-CRM114-Status: GOOD ( 15.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, tglx@linutronix.de, yangyingliang@huawei.com, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Now with 5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"), we can support MBIGEN to generate message based SPIs by writing GICD_SETSPIR. The first 64-pins of each MBIGEN chip is used to generate SPIs, and each MBIGEN chip has several MBIGEN nodes, every node has 128 pins for generating LPIs. The total pins are: 64(SPIs) + 128 * node_nr(LPIs). So we can translate the pin index in a unified way in mbigen_domain_translate(). Also Add TYPE and VEC registers that used by generating SPIs, the driver can access them when MBIGEN is used to generate SPIs. Signed-off-by: Yang Yingliang --- drivers/irqchip/irq-mbigen.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c index f05998f..72db969 100644 --- a/drivers/irqchip/irq-mbigen.c +++ b/drivers/irqchip/irq-mbigen.c @@ -48,6 +48,7 @@ #define MBIGEN_NODE_OFFSET 0x1000 /* offset of vector register in mbigen node */ +#define REG_MBIGEN_SPI_VEC_OFFSET 0x500 #define REG_MBIGEN_LPI_VEC_OFFSET 0x200 /** @@ -62,6 +63,7 @@ * This register is used to configure interrupt * trigger type */ +#define REG_MBIGEN_SPI_TYPE_OFFSET 0x400 #define REG_MBIGEN_LPI_TYPE_OFFSET 0x0 /** @@ -79,6 +81,9 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) { unsigned int nid, pin; + if (hwirq < SPI_NUM_PER_MBIGEN_CHIP) + return (hwirq * 4 + REG_MBIGEN_SPI_VEC_OFFSET); + hwirq -= SPI_NUM_PER_MBIGEN_CHIP; nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; pin = hwirq % IRQS_PER_MBIGEN_NODE; @@ -92,6 +97,13 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq, { unsigned int nid, irq_ofst, ofst; + if (hwirq < SPI_NUM_PER_MBIGEN_CHIP) { + *mask = 1 << (hwirq % 32); + ofst = hwirq / 32 * 4; + *addr = ofst + REG_MBIGEN_SPI_TYPE_OFFSET; + return; + } + hwirq -= SPI_NUM_PER_MBIGEN_CHIP; nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE; @@ -162,14 +174,22 @@ static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) u32 val; base += get_mbigen_vec_reg(d->hwirq); + + /* + * The address of GICD_SETSPI_NSR and GITS_TRANSLATER + * is encoded in mbigen register by default. So,we don't + * need to program the doorbell address at here. + */ + if (d->hwirq < SPI_NUM_PER_MBIGEN_CHIP) { + writel_relaxed(msg->data, base); + return; + } + val = readl_relaxed(base); val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT); val |= (msg->data << IRQ_EVENT_ID_SHIFT); - /* The address of doorbell is encoded in mbigen register by default - * So,we don't need to program the doorbell address at here - */ writel_relaxed(val, base); } @@ -182,8 +202,7 @@ static int mbigen_domain_translate(struct irq_domain *d, if (fwspec->param_count != 2) return -EINVAL; - if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) || - (fwspec->param[0] < SPI_NUM_PER_MBIGEN_CHIP)) + if (fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) return -EINVAL; else *hwirq = fwspec->param[0];