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Dong" To: "linux-arm-kernel@lists.infradead.org" Subject: [PATCH V3 05/10] dt-bindings: pinctrl: imx7ulp: back to imx legacy binding for consistency Thread-Topic: [PATCH V3 05/10] dt-bindings: pinctrl: imx7ulp: back to imx legacy binding for consistency Thread-Index: AQHUcSgNoxDEi5W+9UKo8tChH+m+LQ== Date: Wed, 31 Oct 2018 14:43:13 +0000 Message-ID: <1540996688-23681-6-git-send-email-aisheng.dong@nxp.com> References: <1540996688-23681-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1540996688-23681-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR03CA0016.apcprd03.prod.outlook.com (2603:1096:203:2e::28) To AM0PR04MB4211.eurprd04.prod.outlook.com (2603:10a6:208:66::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM0PR04MB4052; 6:+8Amp66mgl0t81zAmgsI17C/C46LGOSAeBIPZbz/vMcsKjDL+A+mh6zNu0wOaxXWz+O+9NHSb2Uz8ULLDUKRK0DUxjnfG1U4IT5UX3bsyRSlhwVa7RLhapZa1SdSWoNuZ475lsOVCA3lCMxejoQ0UPKtY4MKOuyL85ksehIkVIew+MRF+/JY2kG8IzbVU+HAntI9A1wAo4z6QmCS48sXzgzEpLW5sPbiEmSRtEYL9HIO9oYKtRZ16mLFpL4WyTtzQvHiK5Kcj18iWri9bF+ABE1XJ6VyJSzL8IV66uqSKxKwhjeqQrb3iRETeLf7uKgue9K6jGLG3UDYyKbVqOLLSlZ0THC7L9rmske3j1y8pu+ZJaI7l4Fs3mC4wLyjMWsNu35UJWtCRNFVpuQKg/i113fyUXkG2/4SDxoVfOQZWXyutk1cCbLlzHD2J019IThfCxO0oJGqAlndCGLK2whuSA==; 5:0n1xDo4BnFmUpmfHuNB+7KxIldksdd26i37xsJuWxlilZxBW3Dm5S7jrMW2gS4cCuVQQU9VR7/vV6linnOyhNWeH/vszcOIUrDU6LFsST+UFzzHB2wt7VQJNnaOhRTvZddhFfQU+WS09wlDuM9avFrk/NfSxzktgBNnpWcWxDIM=; 7:qKw1QjupR3DkmolLixVlkNjlCF2q+3Sg4Gd9s4huMDyZMpLp6RA6kHELoCMEpmj2HmIUuzXfPfENLZE9gMEBA3UiEdr8D57Lz/e5FxBTOdDTL02sYinW6q7/yh9k4g4fI83fr4dxZqvjvDtOeC/kcw== x-ms-office365-filtering-correlation-id: 996c2fd1-6dbe-4fd7-ec4e-08d63f3f2f95 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4052; x-ms-traffictypediagnostic: AM0PR04MB4052: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(9452136761055)(269456686620040)(185117386973197); x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(3231382)(944501410)(52105095)(10201501046)(3002001)(6055026)(148016)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123560045)(20161123564045)(20161123558120)(20161123562045)(201708071742011)(7699051)(76991095); SRVR:AM0PR04MB4052; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4052; x-forefront-prvs: 084285FC5C x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(396003)(376002)(366004)(346002)(39860400002)(136003)(189003)(199004)(54534003)(11346002)(99286004)(26005)(316002)(7416002)(305945005)(66066001)(2900100001)(386003)(6506007)(7736002)(575784001)(102836004)(86362001)(2616005)(36756003)(476003)(71190400001)(71200400001)(446003)(6116002)(186003)(97736004)(76176011)(54906003)(52116002)(3846002)(5250100002)(486006)(2501003)(2906002)(50226002)(8936002)(106356001)(8676002)(14454004)(81156014)(81166006)(39060400002)(68736007)(6512007)(6436002)(6486002)(105586002)(6916009)(2351001)(4326008)(478600001)(53936002)(5660300001)(256004)(25786009)(14444005)(5640700003); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4052; H:AM0PR04MB4211.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: GScBOMZ8zuBo7IxI7MUH4ksp+LOUMbfbDYCe+0d7gNVMu+EiLg38rl5mRS/zC8swy2hE40PM21Mod+W1bwqAMjN+BpLBeA2xMjCcU13D6VHRs+cfK8m0YUKNc2c9tfiw0fJQf/iS1bAJAs31A0kmVFSSuetUaDoYZUGIbAR36UFxCYONPUqU81d/3KlUZMsUOJizE9lEZHITbkK1IlIKVSQucNYN33VRzwodCuQ2tKFNk5XTt0Jdkf62f069QkzPGSduR68+LUzolxylZHdcAdjN5/K06yCMgsB4PCXD2oN8xKqGXKC55VMIVMr98kxHTO3IVt12PIQs/31Xx9DKFkPbsZNxmF8Tki5lKeK72JI= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 996c2fd1-6dbe-4fd7-ec4e-08d63f3f2f95 X-MS-Exchange-CrossTenant-originalarrivaltime: 31 Oct 2018 14:43:13.9372 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4052 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181031_074327_109350_73BB67C9 X-CRM114-Status: GOOD ( 16.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "A.s. Dong" , "devicetree@vger.kernel.org" , "dongas86@gmail.com" , Linus Walleij , "linux@armlinux.org.uk" , Stefan Agner , "linux-gpio@vger.kernel.org" , "robh+dt@kernel.org" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , "shawnguo@kernel.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP We already had an earlier conclusion that all new i.MX Socs will keep using the legacy i.MX Pinctrl bindings instead of generic pin config. However, MX7ULP generic pin config binding support has already been in tree before that time. Per SoC maintainers' suggestions, in order to get a better consistency for all i.MX devices, we'd like to go back to imx legacy binding for MX7ULP as well. Cc: Rob Herring Cc: Linus Walleij Cc: Shawn Guo Cc: Stefan Agner Cc: Sascha Hauer Cc: Fabio Estevam Cc: linux-gpio@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Dong Aisheng --- ChangeLog: v3: new patch --- .../bindings/pinctrl/fsl,imx7ulp-pinctrl.txt | 66 ++++++++++------------ 1 file changed, 29 insertions(+), 37 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt index 44ad670a..bfa3703 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt @@ -7,55 +7,47 @@ Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it only supports generic pin config. -Please also refer pinctrl-bindings.txt in this directory for generic pinctrl -binding. - -=== Pin Controller Node === +Please refer to fsl,imx-pinctrl.txt in this directory for common binding +part and usage. Required properties: -- compatible: "fsl,imx7ulp-iomuxc1" -- reg: Should contain the base physical address and size of the iomuxc - registers. - -=== Pin Configuration Node === -- pinmux: One integers array, represents a group of pins mux setting. - The format is pinmux = , PIN_FUNC_ID is a pin working on - a specific function. - - NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux - and config register as follows: - - - Refer to imx7ulp-pinfunc.h in in device tree source folder for all - available imx7ulp PIN_FUNC_ID. - -Optional Properties: -- drive-strength Integer. Controls Drive Strength - 0: Standard - 1: Hi Driver -- drive-push-pull Bool. Enable Pin Push-pull -- drive-open-drain Bool. Enable Pin Open-drian -- slew-rate: Integer. Controls Slew Rate - 0: Standard - 1: Slow -- bias-disable: Bool. Pull disabled -- bias-pull-down: Bool. Pull down on pin -- bias-pull-up: Bool. Pull up on pin +- compatible: "fsl,imx7ulp-iomuxc1". +- fsl,pins: Each entry consists of 5 integers which represents the mux + and config setting for one pin. The first 4 integers + are specified + using a PIN_FUNC_ID macro, which can be found in + imx7ulp-pinfunc.h in the device tree source folder. + The last integer CONFIG is the pad setting value like + pull-up on this pin. + + Please refer to i.MX7ULP Reference Manual for detailed + CONFIG settings. + +CONFIG bits definition: +PAD_CTL_OBE (1 << 17) +PAD_CTL_IBE (1 << 16) +PAD_CTL_LK (1 << 16) +PAD_CTL_DSE_HI (1 << 6) +PAD_CTL_DSE_STD (0 << 6) +PAD_CTL_ODE (1 << 5) +PAD_CTL_PUSH_PULL (0 << 5) +PAD_CTL_SRE_SLOW (1 << 2) +PAD_CTL_SRE_STD (0 << 2) +PAD_CTL_PE (1 << 0) Examples: #include "imx7ulp-pinfunc.h" /* Pin Controller Node */ -iomuxc1: iomuxc@40ac0000 { +iomuxc1: pinctrl@40ac0000 { compatible = "fsl,imx7ulp-iomuxc1"; reg = <0x40ac0000 0x1000>; /* Pin Configuration Node */ pinctrl_lpuart4: lpuart4grp { - pinmux = < - IMX7ULP_PAD_PTC3__LPUART4_RX - IMX7ULP_PAD_PTC2__LPUART4_TX + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x1 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x1 >; - bias-pull-up; }; };