From patchwork Wed Oct 31 23:48:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Reddy X-Patchwork-Id: 10663347 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7046114E2 for ; Wed, 31 Oct 2018 23:49:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 57EEB2B9C0 for ; Wed, 31 Oct 2018 23:49:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4B7CD2B9D3; Wed, 31 Oct 2018 23:49:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C40FB2B9C0 for ; Wed, 31 Oct 2018 23:49:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9/qmAADfjKD/zmI/ZQ/edmhwuR8fxNy7H+agDw8wWs0=; b=U5fa0MT7UVkIpV HV5agPlm/AbaJjU4NSrMXgF/JL8mc0SuptTOr6kIktGcbM6yls6dt0mWUN3U1Cj38yWRuIIUFs82r A3cnJ5+OIV1Nuxw8WluaghZkwHFV4M5KOXRCna5M+IyMI16smanfdrOuzKAWl9wPv2LgJS9Tw2OMw JjaVxD10mw8hxBOidmgxT5Ytp7TgsSz9r95CZZWUF0jvc9/VSKdltAZDjJ9DtfsyaGepp7v8KV1nA ufbilAmNhdf2Vym6d9l8lO/ViSi9a5uXjS2YfdBptgdtJtyDipGb+TB1QKMd6tevK4recG6URFcje oYOOewtAc3DIlIzPOjtQ==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gI0EQ-0001K9-Dr; Wed, 31 Oct 2018 23:49:02 +0000 Received: from hqemgate14.nvidia.com ([216.228.121.143]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gI0EF-00019V-4K for linux-arm-kernel@lists.infradead.org; Wed, 31 Oct 2018 23:48:53 +0000 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 31 Oct 2018 16:48:27 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 31 Oct 2018 16:48:40 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 31 Oct 2018 16:48:40 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 31 Oct 2018 23:48:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 31 Oct 2018 23:48:40 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 31 Oct 2018 16:48:40 -0700 From: Krishna Reddy To: , , Subject: [PATCH v2 2/5] iommu/arm-smmu: Prepare fault, probe, sync functions for sharing code Date: Wed, 31 Oct 2018 16:48:33 -0700 Message-ID: <1541029716-14353-3-git-send-email-vdumpa@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1541029716-14353-2-git-send-email-vdumpa@nvidia.com> References: <1541029716-14353-2-git-send-email-vdumpa@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1541029707; bh=aEAtOrre8PYbKDtJNGI10pa15gCE5D3rp4SrswducyM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=JLkNyNNz/yLZnxBe3yNcVDgjtSjdy8eWbLB3bsIS/lZ24NXB2XsfRbDlp5433lWxJ OlyrQLMaLf0lh14rEZ+LrYCIMg63+08fna+q7EdAF+shbggGKas9x62YFbH0wfTkV6 alnjuHuo44OUeH5gM977Xxq5zaxnMWoZwNKWfI8c2S4MGE3FxtgtbVQIj/DcatpiRU 2qgUohH+rlO/vn2uMXcrydPIWKWD2Rd4nxnLw4k45Wma6iCmxNZr6KosorZEkz7EVL 31wUSFohn82ndYeCHqnf7u3FcJYtkQ9eoJ++68f50rQ9GW0Ctpwx+wPxWY18uRIiAs mE+/4Ok+ewqBg== X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181031_164851_192773_07E14CC5 X-CRM114-Status: GOOD ( 13.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: snikam@nvidia.com, praithatha@nvidia.com, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, talho@nvidia.com, yhsu@nvidia.com, nicolinc@nvidia.com, linux-tegra@vger.kernel.org, treding@nvidia.com, avanbrunt@nvidia.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Prepare fault handling, probe and tlb sync functions to allow sharing code between ARM SMMU driver and Tegra194 SMMU driver. Signed-off-by: Krishna Reddy --- drivers/iommu/arm-smmu-common.c | 53 +++++++++++++++++++++++++++++++++++++++-- drivers/iommu/arm-smmu.c | 42 +++++++------------------------- 2 files changed, 60 insertions(+), 35 deletions(-) diff --git a/drivers/iommu/arm-smmu-common.c b/drivers/iommu/arm-smmu-common.c index 1ad8e5f..0166319 100644 --- a/drivers/iommu/arm-smmu-common.c +++ b/drivers/iommu/arm-smmu-common.c @@ -166,7 +166,7 @@ static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, { unsigned int spin_cnt, delay; - writel_relaxed(0, sync); + writel_relaxed_one(0, sync); for (delay = 1; delay < TLB_LOOP_TIMEOUT; delay *= 2) { for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { if (!(readl_relaxed(status) & sTLBGSTATUS_GSACTIVE)) @@ -287,6 +287,52 @@ static const struct iommu_gather_ops arm_smmu_s2_tlb_ops_v1 = { .tlb_sync = arm_smmu_tlb_sync_vmid, }; +static irqreturn_t arm_smmu_context_fault_common(struct arm_smmu_device *smmu, + struct arm_smmu_cfg *cfg, void __iomem *cb_base) +{ + u32 fsr, fsynr; + unsigned long iova; + + cb_base = ARM_SMMU_CB(smmu, cfg->cbndx); + fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); + + if (!(fsr & FSR_FAULT)) + return IRQ_NONE; + + fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); + iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR); + + dev_err_ratelimited(smmu->dev, + "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n", + fsr, iova, fsynr, cfg->cbndx); + + writel_one(fsr, cb_base + ARM_SMMU_CB_FSR); + return IRQ_HANDLED; +} + +static irqreturn_t arm_smmu_global_fault_common( + struct arm_smmu_device *smmu, void __iomem *gr0_base) +{ + u32 gfsr, gfsynr0, gfsynr1, gfsynr2; + + gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); + gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); + gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); + gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); + + if (!gfsr) + return IRQ_NONE; + + dev_err_ratelimited(smmu->dev, + "Unexpected global fault, this could be serious\n"); + dev_err_ratelimited(smmu->dev, + "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", + gfsr, gfsynr0, gfsynr1, gfsynr2); + + writel_one(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); + return IRQ_HANDLED; +} + static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain, struct io_pgtable_cfg *pgtbl_cfg) { @@ -1757,7 +1803,8 @@ static void arm_smmu_bus_init(void) #endif } -static int arm_smmu_device_probe(struct platform_device *pdev) +static int arm_smmu_device_probe_common(struct platform_device *pdev, + void __iomem **pbase) { struct resource *res; resource_size_t ioaddr; @@ -1786,6 +1833,8 @@ static int arm_smmu_device_probe(struct platform_device *pdev) if (IS_ERR(smmu->base)) return PTR_ERR(smmu->base); smmu->cb_base = smmu->base + resource_size(res) / 2; + if (pbase) + *pbase = smmu->base; num_irqs = 0; while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index a341c9f..d076b3b 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -31,6 +31,8 @@ #include "arm-smmu-common.h" +#define writel_one writel +#define writel_relaxed_one writel_relaxed #include "arm-smmu-common.c" static void arm_smmu_tlb_sync_global(struct arm_smmu_device *smmu) @@ -59,8 +61,6 @@ static void arm_smmu_tlb_sync_context(void *cookie) static irqreturn_t arm_smmu_context_fault(int irq, void *dev) { - u32 fsr, fsynr; - unsigned long iova; struct iommu_domain *domain = dev; struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain); struct arm_smmu_cfg *cfg = &smmu_domain->cfg; @@ -68,44 +68,15 @@ static irqreturn_t arm_smmu_context_fault(int irq, void *dev) void __iomem *cb_base; cb_base = ARM_SMMU_CB(smmu, cfg->cbndx); - fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); - - if (!(fsr & FSR_FAULT)) - return IRQ_NONE; - - fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); - iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR); - - dev_err_ratelimited(smmu->dev, - "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cb=%d\n", - fsr, iova, fsynr, cfg->cbndx); - - writel(fsr, cb_base + ARM_SMMU_CB_FSR); - return IRQ_HANDLED; + return arm_smmu_context_fault_common(smmu, cfg, cb_base); } static irqreturn_t arm_smmu_global_fault(int irq, void *dev) { - u32 gfsr, gfsynr0, gfsynr1, gfsynr2; struct arm_smmu_device *smmu = dev; void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu); - gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); - gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); - gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); - gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); - - if (!gfsr) - return IRQ_NONE; - - dev_err_ratelimited(smmu->dev, - "Unexpected global fault, this could be serious\n"); - dev_err_ratelimited(smmu->dev, - "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", - gfsr, gfsynr0, gfsynr1, gfsynr2); - - writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); - return IRQ_HANDLED; + return arm_smmu_global_fault_common(smmu, gr0_base); } ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU); @@ -125,6 +96,11 @@ static const struct of_device_id arm_smmu_of_match[] = { }; MODULE_DEVICE_TABLE(of, arm_smmu_of_match); +static int arm_smmu_device_probe(struct platform_device *pdev) +{ + return arm_smmu_device_probe_common(pdev, NULL); +} + static struct platform_driver arm_smmu_driver = { .driver = { .name = "arm-smmu",