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[24.205.254.26]) by smtp.gmail.com with ESMTPSA id z6-v6sm8161360pfb.77.2018.11.05.11.06.55 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Nov 2018 11:06:55 -0800 (PST) Message-ID: <1541444814.537.8.camel@sageembedded.com> Subject: [PATCH] mm: improve/fix ARM v7_dma_inv_range() unaligned address handling From: Chris Cole To: linux-arm-kernel@lists.infradead.org Date: Mon, 05 Nov 2018 11:06:54 -0800 Organization: Sage Embedded Software LLC X-Mailer: Evolution 3.26.6 (3.26.6-1.fc27) Mime-Version: 1.0 X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: chris@sageembedded.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch addresses possible memory corruption when v7_dma_inv_range(start_address, end_address) address parameters are not aligned to whole cache lines. This function issues "invalidate" cache management operations to all cache lines from start_address (inclusive) to end_address (exclusive). When start_address and/or end_address are not aligned, the start and/or end cache lines are first issued "clean & invalidate" operation. The assumption is this is done to ensure that any dirty data addresses outside the address range (but part of the first or last cache lines) are cleaned/flushed so that data is not lost, which could happen if just an invalidate is issued. The problem is that these first/last partial cache lines are issued "clean & invalidate" and then "invalidate". This second "invalidate" is not required and worse can cause "lost" writes to addresses outside the address range but part of the cache line. If another component writes to its part of the cache line between the "clean & invalidate" and "invalidate" operations, the write can get lost. This fix is to remove the extra "invalidate" operation when unaligned addressed are used. A kernel module is available that has a stress test to reproduce the issue and a unit test of the updated v7_dma_inv_range(). It can be downloaded from http://ftp.sageembedded.com/outgoing/linux/cache-test-20181102.tgz. v7_dma_inv_range() is call by dmac_[un]map_area(addr, len, direction) when the direction is DMA_FROM_DEVICE. One can (I believe) successfully argue that DMA from a device to main memory should use buffers aligned to cache line size, because the "clean & invalidate" might overwrite data that the device just wrote using DMA. But if a driver does use unaligned buffers, at least this fix will prevent memory corruption outside the buffer. Signed-off-by: chris@sageembedded.com --- arch/arm/mm/cache-v7.S | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 215df435bfb9..4331bdac0686 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -359,18 +359,30 @@ v7_dma_inv_range: ALT_SMP(W(dsb)) ALT_UP(W(nop)) #endif - mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line - + bne 4f +1: tst r1, r3 bic r1, r1, r3 - mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line -1: + bne 5f +2: mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line add r0, r0, r2 cmp r0, r1 - blo 1b + blo 2b +3: dsb st ret lr +4: + mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line + add r0, r0, r2 + cmp r0, r1 + bhs 3b + b 1b +5: + mcr p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line + cmp r0, r1 + bhs 3b + b 2b ENDPROC(v7_dma_inv_range) /*