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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id 12sm8698051pgd.35.2018.11.28.14.01.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 Nov 2018 14:01:26 -0800 (PST) From: Mathieu Poirier To: acme@kernel.org, peterz@infradead.org, mingo@redhat.com Subject: [PATCH v4 4/6] coresight: Use PMU driver configuration for sink selection Date: Wed, 28 Nov 2018 15:01:16 -0700 Message-Id: <1543442478-31465-5-git-send-email-mathieu.poirier@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543442478-31465-1-git-send-email-mathieu.poirier@linaro.org> References: <1543442478-31465-1-git-send-email-mathieu.poirier@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181128_140138_451202_52B8EE80 X-CRM114-Status: GOOD ( 19.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, linux-s390@vger.kernel.org, alexander.shishkin@linux.intel.com, will.deacon@arm.com, hpa@zytor.com, heiko.carstens@de.ibm.com, adrian.hunter@intel.com, ast@kernel.org, suzuki.poulosi@arm.com, linux-arm-kernel@lists.infradead.org, gregkh@linuxfoundation.org, schwidefsky@de.ibm.com, namhyung@kernel.org, tglx@linutronix.de, jolsa@redhat.com, linux-kernel@vger.kernel.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch uses the PMU driver configuration held in event::hw::drv_config to select a sink for each event that is created (the old sysFS way of working is kept around for backward compatibility). By proceeding in this way a sink can be used by multiple sessions without having to play games with entries in sysFS. Signed-off-by: Mathieu Poirier --- drivers/hwtracing/coresight/coresight-etm-perf.c | 58 +++++++++++++++++++----- 1 file changed, 46 insertions(+), 12 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index f21eb28b6782..0fbff912d515 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -177,6 +178,26 @@ static void etm_free_aux(void *data) schedule_work(&event_data->work); } +static struct coresight_device *etm_drv_config_sync(struct perf_event *event) +{ + struct coresight_device *sink = NULL; + struct pmu_drv_config *drv_config = perf_event_get_drv_config(event); + + /* + * Make sure we don't race with perf_drv_config_replace() in + * kernel/events/core.c. + */ + raw_spin_lock(&drv_config->lock); + + /* Copy what we got from user space if applicable. */ + if (drv_config->config) + sink = drv_config->config; + + raw_spin_unlock(&drv_config->lock); + + return sink; +} + static void *etm_setup_aux(struct perf_event *event, void **pages, int nr_pages, bool overwrite) { @@ -190,18 +211,11 @@ static void *etm_setup_aux(struct perf_event *event, void **pages, return NULL; INIT_WORK(&event_data->work, free_event_data); - /* - * In theory nothing prevent tracers in a trace session from being - * associated with different sinks, nor having a sink per tracer. But - * until we have HW with this kind of topology we need to assume tracers - * in a trace session are using the same sink. Therefore go through - * the coresight bus and pick the first enabled sink. - * - * When operated from sysFS users are responsible to enable the sink - * while from perf, the perf tools will do it based on the choice made - * on the cmd line. As such the "enable_sink" flag in sysFS is reset. - */ - sink = coresight_get_enabled_sink(true); + /* First get the sink config from user space. */ + sink = etm_drv_config_sync(event); + if (!sink) + sink = coresight_get_enabled_sink(true); + if (!sink || !sink_ops(sink)->alloc_buffer) goto err; @@ -454,6 +468,25 @@ static void etm_addr_filters_sync(struct perf_event *event) filters->nr_filters = i; } +static void *etm_drv_config_validate(struct perf_event *event, char *cstr) +{ + char drv_config[NAME_MAX]; + struct device *dev; + struct coresight_device *sink; + + strncpy(drv_config, cstr, NAME_MAX); + + /* Look for the device with that name on the CS bus. */ + dev = bus_find_device_by_name(&coresight_bustype, NULL, drv_config); + if (!dev) + return ERR_PTR(-EINVAL); + + sink = to_coresight_device(dev); + put_device(dev); + + return sink; +} + int etm_perf_symlink(struct coresight_device *csdev, bool link) { char entry[sizeof("cpu9999999")]; @@ -498,6 +531,7 @@ static int __init etm_perf_init(void) etm_pmu.addr_filters_sync = etm_addr_filters_sync; etm_pmu.addr_filters_validate = etm_addr_filters_validate; etm_pmu.nr_addr_filters = ETM_ADDR_CMP_MAX; + etm_pmu.drv_config_validate = etm_drv_config_validate; ret = perf_pmu_register(&etm_pmu, CORESIGHT_ETM_PMU_NAME, -1); if (ret == 0)