From patchwork Tue Dec 11 23:29:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 10725275 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id ADA3B17FE for ; Tue, 11 Dec 2018 23:35:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9BC032B4A4 for ; Tue, 11 Dec 2018 23:35:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F2BA2B5D7; Tue, 11 Dec 2018 23:35:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C61732B4A4 for ; Tue, 11 Dec 2018 23:35:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=EABAVOONivSBis4B1o/HlGQknWmyxn+gWUsxf7WohoM=; b=CgFEZNCAPZDMwU wFd11U3Mbfe7nLBlf/HjQOCtA7R0ZkJSXDNcX4HKdo8IDNj1m9tjy5vKODeszYgQ19yNQ+4zjG2Do yotLMuKVAEw4jrb0zS7I9P+OdJu+7Q1o/brcXY0SBXzX3Cod1amYcVJCdheS80Tu1Sh3ytti7WBNb 17S+gYly4USuO9Dm9BHUrVGQHfMeeSKKTzQl0i+Vwv/+kKfa7qrofZDHE2SV/3lGIf1pdjM+hc6OC nD45wigx0DyzM/YxRYx5vXGkf2Huo7r9BIVCutQeLJ41OveydGhHU8jkmji8GxglJxIsTtd4rzZLB EuMP7vn5O2OWUcxg1kPg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gWrZD-0002ue-0o; Tue, 11 Dec 2018 23:35:55 +0000 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70] helo=foss.arm.com) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gWrU4-0004QH-BM for linux-arm-kernel@lists.infradead.org; Tue, 11 Dec 2018 23:30:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4B94580D; Tue, 11 Dec 2018 15:30:36 -0800 (PST) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A15593F614; Tue, 11 Dec 2018 15:30:34 -0800 (PST) From: Dave Martin To: kvmarm@lists.cs.columbia.edu Subject: [RFC PATCH v3 24/24] KVM: arm64/sve: Document KVM API extensions for SVE Date: Tue, 11 Dec 2018 23:29:01 +0000 Message-Id: <1544570941-7377-25-git-send-email-Dave.Martin@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1544570941-7377-1-git-send-email-Dave.Martin@arm.com> References: <1544570941-7377-1-git-send-email-Dave.Martin@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181211_153036_720991_0AAAB077 X-CRM114-Status: GOOD ( 28.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Okamoto Takayuki , Christoffer Dall , Ard Biesheuvel , Marc Zyngier , Catalin Marinas , Will Deacon , =?utf-8?q?Alex_Benn=C3=A9e?= , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds sections to the KVM API documentation describing the extensions for supporting the Scalable Vector Extension (SVE) in guests. Signed-off-by: Dave Martin --- Changes since RFC v2: * Fix documentation regarding which SVE Zn register bits must be accessed in order to get at Vn on an SVE-enabled vcpu. * Update documentation to describe KVM_VM_TYPE_ARM_SVE and related API changes. * Move comment about max_vq==0 semantics for KVM_ARM_SVE_CONFIG_GET to the correct place. * Miscellaneous wording updates to describe the new initialisation semantics. The documentation remains inaccurate / misleading in places. Since the current API design is still needs discussion I expect another respin with API changes. I didn't want to waste effort on a time-consuming documentation rewrite in the meantime. --- Documentation/virtual/kvm/api.txt | 176 +++++++++++++++++++++++++++++++++++++- 1 file changed, 173 insertions(+), 3 deletions(-) diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 5f3c525..2a0605d 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -154,6 +154,13 @@ size of the address translated by the stage2 level (guest physical to host physical address translations). +Also on arm64, if capability KVM_CAP_ARM_SVE is present then the +KVM_VM_TYPE_ARM_SVE flag may be set in the machine type identifier to +enable the KVM API extensions for the Arm Scalable Vector Extension +(SVE) for the created VM. This is required in order to create vcpus +that support SVE. See section 4.117 (KVM_ARM_SVE_CONFIG) for details. + + 4.3 KVM_GET_MSR_INDEX_LIST, KVM_GET_MSR_FEATURE_INDEX_LIST Capability: basic, KVM_CAP_GET_MSR_FEATURES for KVM_GET_MSR_FEATURE_INDEX_LIST @@ -2099,13 +2106,21 @@ Specifically: 0x6030 0000 0010 004c SPSR_UND 64 spsr[KVM_SPSR_UND] 0x6030 0000 0010 004e SPSR_IRQ 64 spsr[KVM_SPSR_IRQ] 0x6060 0000 0010 0050 SPSR_FIQ 64 spsr[KVM_SPSR_FIQ] - 0x6040 0000 0010 0054 V0 128 fp_regs.vregs[0] - 0x6040 0000 0010 0058 V1 128 fp_regs.vregs[1] + 0x6040 0000 0010 0054 V0 128 fp_regs.vregs[0] (*) + 0x6040 0000 0010 0058 V1 128 fp_regs.vregs[1] (*) ... - 0x6040 0000 0010 00d0 V31 128 fp_regs.vregs[31] + 0x6040 0000 0010 00d0 V31 128 fp_regs.vregs[31] (*) 0x6020 0000 0010 00d4 FPSR 32 fp_regs.fpsr 0x6020 0000 0010 00d5 FPCR 32 fp_regs.fpcr +(*) These encodings are not accepted for SVE-enabled vcpus. See + KVM_ARM_SVE_CONFIG for details of how SVE support is configured for + a vcpu. + + The equivalent register content can be accessed via bits [127:0] of + the corresponding SVE Zn registers instead for vcpus that have SVE + enabled (see below). + arm64 CCSIDR registers are demultiplexed by CSSELR value: 0x6020 0000 0011 00 @@ -2115,6 +2130,14 @@ arm64 system registers have the following id bit patterns: arm64 firmware pseudo-registers have the following bit pattern: 0x6030 0000 0014 +arm64 SVE registers have the following bit patterns: + 0x6080 0000 0015 00 Zn bits[2048*slice + 2047 : 2048*slice] + 0x6050 0000 0015 04 Pn bits[256*slice + 255 : 256*slice] + 0x6050 0000 0015 060 FFR bits[256*slice + 255 : 256*slice] + + These registers are only accessible on SVE-enabled vcpus. See + KVM_ARM_SVE_CONFIG for details. + MIPS registers are mapped using the lower 32 bits. The upper 16 of that is the register group type: @@ -2632,6 +2655,8 @@ Parameters: struct kvm_vcpu_init (in) Returns: 0 on success; -1 on error Errors:  EINVAL:    the target is unknown, or the combination of features is invalid. + EBADFD: further configuration required before this ioctl (see sections + 4.2 KVM_CREATE_VM, 4.117 KVM_ARM_SVE_CONFIG)  ENOENT:    a features bit specified is unknown. This tells KVM what type of CPU to present to the guest, and what @@ -2694,6 +2719,8 @@ Returns: 0 on success; -1 on error Errors:  E2BIG:     the reg index list is too big to fit in the array specified by             the user (the number required will be written into n). + EBADFD: (arm64) further configuration required before this ioctl (see + sections 4.2 KVM_CREATE_VM, 4.117 KVM_ARM_SVE_CONFIG) struct kvm_reg_list { __u64 n; /* number of registers in reg[] */ @@ -3777,6 +3804,149 @@ Coalesced pio is based on coalesced mmio. There is little difference between coalesced mmio and pio except that coalesced pio records accesses to I/O ports. +4.117 KVM_ARM_SVE_CONFIG + +Capability: KVM_CAP_ARM_SVE +Architectures: arm64 +Type: vm and vcpu ioctl +Parameters: struct kvm_sve_vls (in/out) +Returns: 0 on success +Errors: + EINVAL: Unrecognised subcommand or bad arguments, or SVE API not enabled + (see section 2.4, KVM_CREATE_VM) + EBADFD: vcpu in wrong state for request + (KVM_ARM_SVE_CONFIG_SET, KVM_ARM_SVE_CONFIG_SET) + ENOMEM: Out of memory + EFAULT: Bad user address + +struct kvm_sve_vls { + __u16 cmd; + __u16 max_vq; + __u16 _reserved[2]; + __u64 required_vqs[8]; +}; + +General: + +In addition to requiring KVM_CAP_ARM_SVE, this ioctl is only available +when the SVE API extensions have been enabled by creating the +corresponding VM with the KVM_VM_TYPE_ARM_SVE flag. See section 4.2 +(KVM_CREATE_VM) for details. + +This should be the first vcpu ioctl issued after creating the vcpu via +KVM_CREATE_VCPU: until SVE configuration for the vcpu is completed via a +successful KVM_ARM_SVE_CONFIG_SET subcommand (see below), non-trivial +vcpu ioctls will be rejected with EBADFD or another appropriate error. + +Parameters: + +cmd: This ioctl supports a few different subcommands, selected by the +value of cmd (described in detail in the following sections). + +_reserved[]: these fields may be meaningful to later kernels. For +forward compatibility, they must be zeroed before invoking this ioctl +for the first time on a given struct kvm_sve_vls object. (So, memset() +it to zero before first use, or allocate with calloc() for example.) + +max_vq, required_vqs[]: + +If max_vq == 0, SVE is disabled for this vcpu. + +Otherwise, max_vq and required_vqs[] encode a set of SVE vector +lengths to attempt to configure for this vcpu. The set is encoded as +follows: + +If (a * 64 + b + 1) <= max_vq, then the bit represented by + + required_vqs[a] & ((__u64)1 << b) + +(where a is in the range 0..7 and b is in the range 0..63) +indicates that the vector length (a * 64 + b + 1) * 128 bits is +supported (KVM_ARM_SVE_CONFIG_QUERY, KVM_ARM_SVE_CONFIG_GET) or required +(KVM_ARM_SVE_CONFIG_SET). + +If (a * 64 + b + 1) > max_vq, then the vector length +(a * 64 + b + 1) * 128 bits is unsupported or prohibited respectively. +In other words, only the first max_vq bits in required_vqs[] are +significant; remaining bits are implicitly treated as if they were zero. + +max_vq must be in the range SVE_VQ_MIN (1) to SVE_VQ_MAX (512). + +See Documentation/arm64/sve.txt for an explanation of vector lengths and +the meaning associated with "VQ". + +Subcommands: + +/* values for cmd: */ +#define KVM_ARM_SVE_CONFIG_QUERY 0 /* query what the host can support */ +#define KVM_ARM_SVE_CONFIG_SET 1 /* enable SVE for vcpu and set VLs */ +#define KVM_ARM_SVE_CONFIG_GET 2 /* read the set of VLs for a vcpu */ + +Subcommand details: + +4.117.1 KVM_ARM_SVE_CONFIG_QUERY +Type: vm and vcpu + +Retrieve the full set of SVE vector lengths available for use by KVM +guests on this host. The result is independent of which vcpu this +command is invoked on. As a convenience, it may also be invoked on a +vm file descriptor, eliminating the need to create a vcpu first. + +4.117.2 KVM_ARM_SVE_CONFIG_SET +Type: vcpu only + +Sets whether SVE is enabled for the vcpu, and if so sets the set of +SVE vector lengths that will be visible to the guest. + +This is the only way to enable SVE for a vcpu: if this command is not +invoked for a vcpu then SVE will not be available to the guest on this +vcpu. + +This subcommand is only permitted once per vcpu, before KVM_RUN has been +invoked for the vcpu for the first time. Otherwise, the command fails +with -EBADFD and the state of the vcpu is not modified. + +In typical use, the user should call KVM_ARM_SVE_CONFIG_QUERY first to +populate a struct kvm_sve_vls with the full set of vector lengths +available on the host, then set cmd = KVM_ARM_SVE_CONFIG_SET and +re-issue the KVM_ARM_SVE_CONFIG ioctl on the desired vcpu. This will +configure the best set of vector lengths available. When following this +approach, the maximum available vector length can also be restricted by +reducing the value of max_vq before invoking KVM_ARM_SVE_CONFIG_SET. + +Every requested vector length in the struct kvm_sve_vls argument must be +supported by the hardware. In addition, except for vector lengths +greater than the maximum requested vector length, every vector length +not requested must *not* be supported by the hardware. (The latter +restriction may be relaxed in the future.) If the requested set of +vector lengths is not supportable, the command fails with -EINVAL and +the state of the vcpu is not modified. + +Different vcpus of a vm may be configured with different sets of vector +lengths. Equally, some vcpus may have SVE enabled and some not. +However, such configurations are not recommended except for testing and +experimentation purposes. Architecturally compliant guest OSes will +work, but may or may not make effective use of the resulting +configuration. + +After a successful KVM_ARM_SVE_CONFIG_SET, KVM_ARM_SVE_CONFIG_GET can be +used to retrieve the configured set of vector lengths. + +4.117.3 KVM_ARM_SVE_CONFIG_GET +Type: vcpu only + +This subcommand returns the set of vector lengths enabled for the vcpu. +SVE must have been disabled or enabled and configured for this vcpu by a +successful prior KVM_ARM_SVE_CONFIG_SET call. Otherwise, -EBADFD is +returned. + +If SVE is disabled for this vcpu, this subcommand will yield +max_vq == 0; otherwise max_vq and required_vqs[] indicate the +(non-empty) set of configured vector lengths. + +The state of the vcpu is unchanged. + + 5. The kvm_run structure ------------------------