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Thu, 20 Dec 2018 07:49:46 +0000 From: BOUGH CHEN To: "ulf.hansson@linaro.org" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kernel@pengutronix.de" , Fabio Estevam , "adrian.hunter@intel.com" Subject: [PATCH 2/3] mmc: sdhci-esdhc-imx: add SD clock limitation for imx6ull Thread-Topic: [PATCH 2/3] mmc: sdhci-esdhc-imx: add SD clock limitation for imx6ull Thread-Index: AQHUmDiTyHn+7tGsDkmINmEMtso26w== Date: Thu, 20 Dec 2018 07:49:46 +0000 Message-ID: <1545292612-14471-2-git-send-email-haibo.chen@nxp.com> References: <1545292612-14471-1-git-send-email-haibo.chen@nxp.com> In-Reply-To: <1545292612-14471-1-git-send-email-haibo.chen@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 1.9.1 x-clientproxiedby: HK0PR03CA0025.apcprd03.prod.outlook.com (2603:1096:203:2f::13) To VI1PR04MB5040.eurprd04.prod.outlook.com (2603:10a6:803:59::33) authentication-results: spf=none (sender IP is ) smtp.mailfrom=haibo.chen@nxp.com; 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And for eMMC DDR52 and SD/SDIO DDR50 mode, the clock rate can't exceed 45MHz. This patch add this limit for imx6ull. Signed-off-by: Haibo Chen Acked-by: Adrian Hunter Nacked-by: Russell King --- drivers/mmc/host/sdhci-esdhc-imx.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index d0d3193..75a2484 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -138,7 +138,11 @@ #define ESDHC_FLAG_HS200 BIT(8) /* The IP supports HS400 mode */ #define ESDHC_FLAG_HS400 BIT(9) - +/* The IP has errata ERR010450 + * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't + * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. + */ +#define ESDHC_FLAG_ERR010450 BIT(10) /* A clock frequency higher than this rate requires strobe dll control */ #define ESDHC_STROBE_DLL_CLK_FREQ 100000000 @@ -177,6 +181,12 @@ struct esdhc_soc_data { | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, }; +static struct esdhc_soc_data usdhc_imx6ull_data = { + .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING + | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 + | ESDHC_FLAG_ERR010450, +}; + static struct esdhc_soc_data usdhc_imx7d_data = { .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 @@ -227,6 +237,7 @@ struct pltfm_imx_data { { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, + { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, { /* sentinel */ } }; @@ -733,6 +744,12 @@ static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, | ESDHC_CLOCK_MASK); sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); + if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { + if (imx_data->is_ddr) + clock = clock > 45000000 ? 45000000 : clock; + else + clock = clock > 150000000 ? 150000000 : clock; + while (host_clock / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256) pre_div *= 2;