From patchwork Fri Feb 8 12:26:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 10802995 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0F14513A4 for ; Fri, 8 Feb 2019 12:26:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EF7C42DCC9 for ; Fri, 8 Feb 2019 12:25:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E370F2DD09; Fri, 8 Feb 2019 12:25:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 538272DCC9 for ; Fri, 8 Feb 2019 12:25:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:Message-Id:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=Luc6uQHEt6bkq0R9sqY6MstndKi6+dS106qVZLuwM14=; b=AGh 19gh1t5TiCyF3x1TWCikyAGMcI2Kk9udsynO811qZTkJD3m2TvMhTrUMYfnu27a0LWpppeFtsHUt/ BW+OJrqkIw95g4vHEVZmVctwREmtPzcBB+0Wzdc6Bx1W6+c7TwaOxHNisGw5BRI7j5qluQ+BIzWsP Jp3DzfgPEhXtNfTvLNi+OA0jfWdCM73KO81+eDM2ldAd6MZaXkyuYAiU0O9vVFy5BZ3u5EhhwZKxi 5EOtl27lW43RD9XQlA3ZfnrNBgVCZ+91WJli8MRkV3BNIHwVNLJ3U6pQPghbDgDAGDQbGvDjxU+Z8 xnomhNsz05MGbhtgUbOzFlA4GdOn7Zg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5EC-0007WL-NQ; Fri, 08 Feb 2019 12:25:56 +0000 Received: from mx.socionext.com ([202.248.49.38]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gs5Ds-0007A4-Cq for linux-arm-kernel@lists.infradead.org; Fri, 08 Feb 2019 12:25:53 +0000 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 08 Feb 2019 21:25:35 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 6FBE160062; Fri, 8 Feb 2019 21:25:35 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 8 Feb 2019 21:25:35 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 498921A04E1; Fri, 8 Feb 2019 21:25:35 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 2E5511202F1; Fri, 8 Feb 2019 21:25:35 +0900 (JST) From: Sugaya Taichi To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC Date: Fri, 8 Feb 2019 21:26:18 +0900 Message-Id: <1549628778-30785-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190208_042537_438747_26EC418E X-CRM114-Status: GOOD ( 19.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shinji Kanematsu , Masami Hiramatsu , Sugaya Taichi , Russell King , Jassi Brar , Takao Orito , Kazuhiro Kasai MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP This adds the basic M10V SoC support under arch/arm. Since all cores are activated in the custom bootloader before booting linux, it is necessary to wait for the secondary-cores using cpu-enable- method and special sram. Signed-off-by: Sugaya Taichi --- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-milbeaut/Kconfig | 20 ++++++ arch/arm/mach-milbeaut/Makefile | 1 + arch/arm/mach-milbeaut/platsmp.c | 144 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 168 insertions(+) create mode 100644 arch/arm/mach-milbeaut/Kconfig create mode 100644 arch/arm/mach-milbeaut/Makefile create mode 100644 arch/arm/mach-milbeaut/platsmp.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 664e918..c8cb752 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -750,6 +750,8 @@ source "arch/arm/mach-mediatek/Kconfig" source "arch/arm/mach-meson/Kconfig" +source "arch/arm/mach-milbeaut/Kconfig" + source "arch/arm/mach-mmp/Kconfig" source "arch/arm/mach-moxart/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 9db3c58..00000e9 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0 machine-$(CONFIG_ARCH_MVEBU) += mvebu machine-$(CONFIG_ARCH_MXC) += imx machine-$(CONFIG_ARCH_MEDIATEK) += mediatek +machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut machine-$(CONFIG_ARCH_MXS) += mxs machine-$(CONFIG_ARCH_NETX) += netx machine-$(CONFIG_ARCH_NOMADIK) += nomadik diff --git a/arch/arm/mach-milbeaut/Kconfig b/arch/arm/mach-milbeaut/Kconfig new file mode 100644 index 0000000..6a576fd --- /dev/null +++ b/arch/arm/mach-milbeaut/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0 +menuconfig ARCH_MILBEAUT + bool "Socionext Milbeaut SoCs" + depends on ARCH_MULTI_V7 + select ARM_GIC + help + This enables support for Socionext Milbeaut SoCs + +if ARCH_MILBEAUT + +config ARCH_MILBEAUT_M10V + bool "Milbeaut SC2000/M10V platform" + select ARM_ARCH_TIMER + select MILBEAUT_TIMER + select PINCTRL + select PINCTRL_MILBEAUT + help + Support for Socionext's MILBEAUT M10V based systems + +endif diff --git a/arch/arm/mach-milbeaut/Makefile b/arch/arm/mach-milbeaut/Makefile new file mode 100644 index 0000000..ce5ea06 --- /dev/null +++ b/arch/arm/mach-milbeaut/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-milbeaut/platsmp.c b/arch/arm/mach-milbeaut/platsmp.c new file mode 100644 index 0000000..bdcd98e --- /dev/null +++ b/arch/arm/mach-milbeaut/platsmp.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright: (C) 2018 Socionext Inc. + * Copyright: (C) 2015 Linaro Ltd. + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define M10V_MAX_CPU 4 +#define KERNEL_UNBOOT_FLAG 0x12345678 + +static void __iomem *m10v_smp_base; + +static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle) +{ + unsigned int mpidr, cpu, cluster; + + if (!m10v_smp_base) + return -ENXIO; + + mpidr = cpu_logical_map(l_cpu); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + + if (cpu >= M10V_MAX_CPU) + return -EINVAL; + + pr_info("%s: cpu %u l_cpu %u cluster %u\n", + __func__, cpu, l_cpu, cluster); + + writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4); + arch_send_wakeup_ipi_mask(cpumask_of(l_cpu)); + + return 0; +} + +static void m10v_smp_init(unsigned int max_cpus) +{ + unsigned int mpidr, cpu, cluster; + struct device_node *np; + + np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram"); + if (!np) + return; + + m10v_smp_base = of_iomap(np, 0); + if (!m10v_smp_base) + return; + + mpidr = read_cpuid_mpidr(); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); + pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster); + + for (cpu = 0; cpu < M10V_MAX_CPU; cpu++) + writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4); +} + +static void m10v_cpu_die(unsigned int l_cpu) +{ + gic_cpu_if_down(0); + v7_exit_coherency_flush(louis); + wfi(); +} + +static int m10v_cpu_kill(unsigned int l_cpu) +{ + unsigned int mpidr, cpu; + + mpidr = cpu_logical_map(l_cpu); + cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); + + writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4); + + return 1; +} + +static struct smp_operations m10v_smp_ops __initdata = { + .smp_prepare_cpus = m10v_smp_init, + .smp_boot_secondary = m10v_boot_secondary, + .cpu_die = m10v_cpu_die, + .cpu_kill = m10v_cpu_kill, +}; +CPU_METHOD_OF_DECLARE(m10v_smp, "socionext,milbeaut-m10v-smp", &m10v_smp_ops); + +static int m10v_pm_valid(suspend_state_t state) +{ + return (state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM); +} + +typedef void (*phys_reset_t)(unsigned long); +static phys_reset_t phys_reset; + +static int m10v_die(unsigned long arg) +{ + setup_mm_for_reboot(); + asm("wfi"); + /* Boot just like a secondary */ + phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset); + phys_reset(virt_to_phys(cpu_resume)); + + return 0; +} + +static int m10v_pm_enter(suspend_state_t state) +{ + switch (state) { + case PM_SUSPEND_STANDBY: + pr_err("STANDBY\n"); + asm("wfi"); + break; + case PM_SUSPEND_MEM: + pr_err("SUSPEND\n"); + cpu_pm_enter(); + cpu_suspend(0, m10v_die); + cpu_pm_exit(); + break; + } + return 0; +} + +static const struct platform_suspend_ops m10v_pm_ops = { + .valid = m10v_pm_valid, + .enter = m10v_pm_enter, +}; + +struct clk *m10v_clclk_register(struct device *cpu_dev); + +static int __init m10v_pm_init(void) +{ + suspend_set_ops(&m10v_pm_ops); + + return 0; +} +late_initcall(m10v_pm_init);