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Fri, 15 Feb 2019 18:07:22 +0000 From: Abel Vesa To: Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Lucas Stach , Angus Ainslie Subject: [PATCH v2 1/3] arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores Thread-Topic: [PATCH v2 1/3] arm64: dts: imx8mq: Add the clocks and the latencies for the A53 cores Thread-Index: AQHUxVlMOnMGYj2UEkGIzXXdUVdTXw== Date: Fri, 15 Feb 2019 18:07:22 +0000 Message-ID: <1550254032-16451-2-git-send-email-abel.vesa@nxp.com> References: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> In-Reply-To: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR0502CA0043.eurprd05.prod.outlook.com (2603:10a6:20b:56::20) To AM0PR04MB5779.eurprd04.prod.outlook.com (2603:10a6:208:131::23) x-originating-ip: [95.76.156.53] authentication-results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 27cef4af-9b29-4796-d058-08d693706e84 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 9155bd4..1a89062 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -87,6 +87,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x0>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; @@ -95,6 +97,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x1>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; @@ -103,6 +107,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x2>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; }; @@ -111,6 +117,8 @@ device_type = "cpu"; compatible = "arm,cortex-a53"; reg = <0x3>; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; };