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Fri, 15 Feb 2019 18:07:24 +0000 From: Abel Vesa To: Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Lucas Stach , Angus Ainslie Subject: [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties Thread-Topic: [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores opp properties Thread-Index: AQHUxVlNIq31A6OcskGGyy1wv+2NnQ== Date: Fri, 15 Feb 2019 18:07:24 +0000 Message-ID: <1550254032-16451-4-git-send-email-abel.vesa@nxp.com> References: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> In-Reply-To: <1550254032-16451-1-git-send-email-abel.vesa@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM6PR0502CA0043.eurprd05.prod.outlook.com (2603:10a6:20b:56::20) To AM0PR04MB5779.eurprd04.prod.outlook.com (2603:10a6:208:131::23) x-originating-ip: [95.76.156.53] authentication-results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 08f99247-b403-46cf-8468-08d693706fbf x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; 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According to the datasheet: https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf section 3.1.3 Operating ranges. The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V. The 1GHz runs in overdrive mode with the regulator set to 1V. Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 1a89062..ebdec9e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -91,6 +91,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_1: cpu@1 { @@ -101,6 +102,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_2: cpu@2 { @@ -111,6 +113,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_3: cpu@3 { @@ -121,6 +124,7 @@ clocks = <&clk IMX8MQ_CLK_ARM>; enable-method = "psci"; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_0_opp_table>; }; A53_L2: l2-cache0 { @@ -666,6 +670,25 @@ status = "disabled"; }; + + a53_0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + clock-latency-ns = <150000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */