| Message ID | 1550662986-40987-2-git-send-email-vladimir.murzin@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] arm64: virt: Relax GIC version check | expand |
On Wed, 20 Feb 2019 11:43:06 +0000 Vladimir Murzin <vladimir.murzin@arm.com> wrote: + Russell, > arm64 has got relaxation on GIC version check at early boot stage due > to update of the GIC architecture let's align ARM with that. > > To help backports (even though the code was correct at the time of writing) > Fixes: e59941b9b3817c9b1dd6662d903150fe3f3c3b0b ("ARM: 8527/1: virt: enable GICv3 system registers") > > Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> > --- > arch/arm/kernel/hyp-stub.S | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S > index 9ef1759..fd0a723 100644 > --- a/arch/arm/kernel/hyp-stub.S > +++ b/arch/arm/kernel/hyp-stub.S > @@ -179,8 +179,8 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE > @ Check whether GICv3 system registers are available > mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 > ubfx r7, r7, #28, #4 > - cmp r7, #1 > - bne 2f > + teq r7, #0 > + beq 2f > > @ Enable system register accesses > mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Can you please put this in Russell's patch system? Thanks, M.
On 2/20/19 1:50 PM, Marc Zyngier wrote: > On Wed, 20 Feb 2019 11:43:06 +0000 > Vladimir Murzin <vladimir.murzin@arm.com> wrote: > > + Russell, > >> arm64 has got relaxation on GIC version check at early boot stage due >> to update of the GIC architecture let's align ARM with that. >> >> To help backports (even though the code was correct at the time of writing) >> Fixes: e59941b9b3817c9b1dd6662d903150fe3f3c3b0b ("ARM: 8527/1: virt: enable GICv3 system registers") >> >> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> >> --- >> arch/arm/kernel/hyp-stub.S | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S >> index 9ef1759..fd0a723 100644 >> --- a/arch/arm/kernel/hyp-stub.S >> +++ b/arch/arm/kernel/hyp-stub.S >> @@ -179,8 +179,8 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE >> @ Check whether GICv3 system registers are available >> mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 >> ubfx r7, r7, #28, #4 >> - cmp r7, #1 >> - bne 2f >> + teq r7, #0 >> + beq 2f >> >> @ Enable system register accesses >> mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE > > Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> > > Can you please put this in Russell's patch system? Patch #8848 Cheers Vladimir > > Thanks, > > M. >
diff --git a/arch/arm/kernel/hyp-stub.S b/arch/arm/kernel/hyp-stub.S index 9ef1759..fd0a723 100644 --- a/arch/arm/kernel/hyp-stub.S +++ b/arch/arm/kernel/hyp-stub.S @@ -179,8 +179,8 @@ ARM_BE8(orr r7, r7, #(1 << 25)) @ HSCTLR.EE @ Check whether GICv3 system registers are available mrc p15, 0, r7, c0, c1, 1 @ ID_PFR1 ubfx r7, r7, #28, #4 - cmp r7, #1 - bne 2f + teq r7, #0 + beq 2f @ Enable system register accesses mrc p15, 4, r7, c12, c9, 5 @ ICC_HSRE
arm64 has got relaxation on GIC version check at early boot stage due to update of the GIC architecture let's align ARM with that. To help backports (even though the code was correct at the time of writing) Fixes: e59941b9b3817c9b1dd6662d903150fe3f3c3b0b ("ARM: 8527/1: virt: enable GICv3 system registers") Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> --- arch/arm/kernel/hyp-stub.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)