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Mon, 4 Mar 2019 11:17:14 +0100 Received: from lmecxl0923.lme.st.com (10.48.0.237) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 4 Mar 2019 11:17:13 +0100 From: Ludovic Barre To: Ulf Hansson , Rob Herring Subject: [PATCH 4/5] mmc: mmci: stm32: define get_dctrl_cfg Date: Mon, 4 Mar 2019 11:17:04 +0100 Message-ID: <1551694625-6414-5-git-send-email-ludovic.Barre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1551694625-6414-1-git-send-email-ludovic.Barre@st.com> References: <1551694625-6414-1-git-send-email-ludovic.Barre@st.com> MIME-Version: 1.0 X-Originating-IP: [10.48.0.237] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-03-04_04:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190304_021721_566344_D4B14232 X-CRM114-Status: GOOD ( 12.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Alexandre Torgue , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, srinivas.kandagatla@linaro.org, Ludovic Barre , Maxime Coquelin , linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: Ludovic Barre This patch defines get_dctrl_cfg callback for sdmmc variant. sdmmc variant has specific stm32 transfer modes. sdmmc data transfer mode selection could be: -Block data transfer ending on block count. -SDIO multibyte data transfer. -MMC Stream data transfer (not used). -Block data transfer ending with STOP_TRANSMISSION command. Signed-off-by: Ludovic Barre --- drivers/mmc/host/mmci.h | 5 +++++ drivers/mmc/host/mmci_stm32_sdmmc.c | 21 +++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 6f28f71..eb5d99af 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -131,6 +131,11 @@ /* Control register extensions in the Qualcomm versions */ #define MCI_DPSM_QCOM_DATA_PEND BIT(17) #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20) +/* Control register extensions in STM32 versions */ +#define MCI_DPSM_STM32_MODE_BLOCK (0 << 2) +#define MCI_DPSM_STM32_MODE_SDIO (1 << 2) +#define MCI_DPSM_STM32_MODE_STREAM (2 << 2) +#define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2) #define MMCIDATACNT 0x030 #define MMCISTATUS 0x034 diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c index cfbfc6f..e7bf744 100644 --- a/drivers/mmc/host/mmci_stm32_sdmmc.c +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c @@ -265,10 +265,31 @@ static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr) } } +u32 sdmmc_get_dctrl_cfg(struct mmci_host *host) +{ + struct variant_data *variant = host->variant; + int blksz_bits; + u32 datactrl; + + blksz_bits = ffs(host->data->blksz) - 1; + datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4; + + if (host->mmc->card && mmc_card_sdio(host->mmc->card) && + host->data->blocks == 1) + datactrl |= MCI_DPSM_STM32_MODE_SDIO; + else if (host->data->stop && !host->mrq->sbc) + datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP; + else + datactrl |= MCI_DPSM_STM32_MODE_BLOCK; + + return datactrl; +} + static struct mmci_host_ops sdmmc_variant_ops = { .validate_data = sdmmc_idma_validate_data, .prep_data = sdmmc_idma_prep_data, .unprep_data = sdmmc_idma_unprep_data, + .get_datactrl_cfg = sdmmc_get_dctrl_cfg, .dma_setup = sdmmc_idma_setup, .dma_start = sdmmc_idma_start, .dma_finalize = sdmmc_idma_finalize,