From patchwork Fri Mar 8 05:49:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daoyuan Huang X-Patchwork-Id: 10844227 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 06FE61803 for ; Fri, 8 Mar 2019 05:50:37 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E2CF62E05E for ; Fri, 8 Mar 2019 05:50:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D63812E068; Fri, 8 Mar 2019 05:50:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 47CEF2E064 for ; Fri, 8 Mar 2019 05:50:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Ug7heJpweqtIK7EbYog/0fm6XNf39UUrCjmvkV3OLxc=; b=ADYYTVpriIxzNL xyZaAo+mgQcfPhGwtapMHA3annZfXmKB5zIXreNHZHLeR1qKEcUEON3W9crHbggLHUMsSYy1/h2TH xL7adK8Q6pvv30bUmeD+tigEBfWJ6G4kWFG1zqqW3s4P901datiNRhMejfkwCRI+cjm0FXbkYHETA E81YyuXbXRzCUg7/fH5BQqkscIteBYGBOqH7FX/N48ou1LwMuv0ZwLbRmhFSbBHA9ii4TiKFVW2cW 1gpm08TMD+TNfkmNb4Ni9FPaUClJ2eflrEZCnYHa6sE2SxsT32dD2lbX81Z5ohCQabg3C25tOSWm8 xtn1+Lyl9TSuZJ/CpKPg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1h28Ov-0003lS-U9; Fri, 08 Mar 2019 05:50:33 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1h28OX-0003EN-Nf; Fri, 08 Mar 2019 05:50:16 +0000 X-UUID: 57a243945cc84459a74208b21494fb31-20190307 X-UUID: 57a243945cc84459a74208b21494fb31-20190307 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLS) with ESMTP id 735499175; Thu, 07 Mar 2019 21:50:02 -0800 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 7 Mar 2019 21:50:00 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 8 Mar 2019 13:49:58 +0800 Received: from mtkslt306.mediatek.inc (10.21.14.136) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 8 Mar 2019 13:49:58 +0800 From: Daoyuan Huang To: , , , , Subject: [RFC v1 1/4] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Date: Fri, 8 Mar 2019 13:49:17 +0800 Message-ID: <1552024160-33055-2-git-send-email-daoyuan.huang@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552024160-33055-1-git-send-email-daoyuan.huang@mediatek.com> References: <1552024160-33055-1-git-send-email-daoyuan.huang@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: D309C3BB325EE5CD1C3EB38F6E03DDAFA3B6E63593EC0FFA1ECC1C6D3F6065172000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190307_215010_003287_08A5FA4B X-CRM114-Status: GOOD ( 10.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Sean.Cheng@mediatek.com, Rynn.Wu@mediatek.com, srv_heupstream@mediatek.com, daoyuan huang , holmes.chiou@mediatek.com, Jerry-ch.Chen@mediatek.com, jungo.lin@mediatek.com, sj.huang@mediatek.com, yuzhao@chromium.org, linux-mediatek@lists.infradead.org, ping-hsun.wu@mediatek.com, zwisler@chromium.org, christie.yu@mediatek.com, frederic.chen@mediatek.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP From: daoyuan huang This patch adds DT binding document for Media Data Path 3 (MDP3) a unit in multimedia system used for scaling and color format convert. Signed-off-by: Ping-Hsun Wu Signed-off-by: daoyuan huang --- .../bindings/media/mediatek,mt8183-mdp3.txt | 217 +++++++++++++++++++++ 1 file changed, 217 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8183-mdp3.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8183-mdp3.txt b/Documentation/devicetree/bindings/media/mediatek,mt8183-mdp3.txt new file mode 100644 index 0000000..cf3e808 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8183-mdp3.txt @@ -0,0 +1,217 @@ +* Mediatek Media Data Path 3 + +Media Data Path 3 (MDP3) is used for scaling and color space conversion. + +Required properties (controller node): +- compatible: "mediatek,mt8183-mdp" +- mediatek,scp: the node of system control processor (SCP), using the + remoteproc & rpmsg framework, see + Documentation/devicetree/bindings/remoteproc/mtk,scp.txt for details. +- mediatek,mmsys: the node of mux(multiplexer) controller for HW connections. +- mediatek,mm-mutex: the node of sof(start of frame) signal controller. +- mediatek,mailbox-gce: the node of global command engine (GCE), used to + read/write registers with critical time limitation, see + Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details. +- mboxes: mailbox number used to communicate with GCE. +- gce-subsys: sub-system id corresponding to the register address. +- gce-event-names: in use event name list, used to correspond to event IDs. +- gce-events: in use event IDs list, all IDs are defined in + 'dt-bindings/gce/mt8183-gce.h'. + +Required properties (all function blocks, child node): +- compatible: Should be one of + "mediatek,mt8183-mdp-rdma" - read DMA + "mediatek,mt8183-mdp-rsz" - resizer + "mediatek,mt8183-mdp-wdma" - write DMA + "mediatek,mt8183-mdp-wrot" - write DMA with rotation + "mediatek,mt8183-mdp-ccorr" - color correction with 3X3 matrix +- reg: Physical base address and length of the function block register space +- clocks: device clocks, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- power-domains: a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details. +- mediatek,mdp-id: HW index to distinguish same functionality modules. + +Required properties (DMA function blocks, child node): +- compatible: Should be one of + "mediatek,mt8183-mdp-rdma" + "mediatek,mt8183-mdp-wdma" + "mediatek,mt8183-mdp-wrot" +- iommus: should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. +- mediatek,larb: must contain the local arbiters in the current Socs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details. + +Required properties (input path selection node): +- compatible: + "mediatek,mt8183-mdp-dl" - MDP direct link input source selection +- reg: Physical base address and length of the function block register space +- clocks: device clocks, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- mediatek,mdp-id: HW index to distinguish same functionality modules. + +Required properties (ISP PASS2 (DIP) module path selection node): +- compatible: + "mediatek,mt8183-mdp-imgi" - input DMA of ISP PASS2 (DIP) module for raw image input +- reg: Physical base address and length of the function block register space +- mediatek,mdp-id: HW index to distinguish same functionality modules. + +Required properties (SW node): +- compatible: Should be one of + "mediatek,mt8183-mdp-exto" - output DMA of ISP PASS2 (DIP) module for yuv image output + "mediatek,mt8183-mdp-path" - MDP output path selection +- mediatek,mdp-id: HW index to distinguish same functionality modules. + +Example: + mdp_camin@14000000 { + compatible = "mediatek,mt8183-mdp-dl"; + mediatek,mdp-id = <0>; + reg = <0 0x14000000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_DL_TXCK>, + <&mmsys CLK_MM_MDP_DL_RX>; + }; + + mdp_camin2@14000000 { + compatible = "mediatek,mt8183-mdp-dl"; + mediatek,mdp-id = <1>; + reg = <0 0x14000000 0 0x1000>; + clocks = <&mmsys CLK_MM_IPU_DL_TXCK>, + <&mmsys CLK_MM_IPU_DL_RX>; + }; + + mdp_rdma0: mdp_rdma0@14001000 { + compatible = "mediatek,mt8183-mdp-rdma", "mediatek,mt8183-mdp3"; + mediatek,scp = <&scp>; + mediatek,mdp-id = <0>; + reg = <0 0x14001000 0 0x1000>; + power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mediatek,larb = <&larb0>; + mediatek,mmsys = <&mmsys>; + mediatek,mm-mutex = <&mutex>; + mediatek,mailbox-gce = <&gce>; + mboxes = <&gce 20 0 CMDQ_THR_PRIO_LOWEST>, + <&gce 21 0 CMDQ_THR_PRIO_LOWEST>, + <&gce 22 0 CMDQ_THR_PRIO_LOWEST>, + <&gce 23 0 CMDQ_THR_PRIO_LOWEST>; + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, + <&gce 0x14010000 SUBSYS_1401XXXX>, + <&gce 0x14020000 SUBSYS_1402XXXX>, + <&gce 0x15020000 SUBSYS_1502XXXX>; + gce-event-names = "rdma0_sof", + "rsz0_sof", + "rsz1_sof", + "tdshp0_sof", + "wrot0_sof", + "wdma0_sof", + "rdma0_done", + "wrot0_done", + "wdma0_done", + "isp_p2_0_done", + "isp_p2_1_done", + "isp_p2_2_done", + "isp_p2_3_done", + "isp_p2_4_done", + "isp_p2_5_done", + "isp_p2_6_done", + "isp_p2_7_done", + "isp_p2_8_done", + "isp_p2_9_done", + "isp_p2_10_done", + "isp_p2_11_done", + "isp_p2_12_done", + "isp_p2_13_done", + "isp_p2_14_done", + "wpe_done", + "wpe_b_done"; + gce-events = <&gce CMDQ_EVENT_MDP_RDMA0_SOF>, + <&gce CMDQ_EVENT_MDP_RSZ0_SOF>, + <&gce CMDQ_EVENT_MDP_RSZ1_SOF>, + <&gce CMDQ_EVENT_MDP_TDSHP_SOF>, + <&gce CMDQ_EVENT_MDP_WROT0_SOF>, + <&gce CMDQ_EVENT_MDP_WDMA0_SOF>, + <&gce CMDQ_EVENT_MDP_RDMA0_EOF>, + <&gce CMDQ_EVENT_MDP_WROT0_EOF>, + <&gce CMDQ_EVENT_MDP_WDMA0_EOF>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_0>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_1>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_2>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_3>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_4>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_5>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_6>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_7>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_8>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_9>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_10>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_11>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_12>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_13>, + <&gce CMDQ_EVENT_ISP_FRAME_DONE_P2_14>, + <&gce CMDQ_EVENT_WPE_A_DONE>, + <&gce CMDQ_EVENT_SPE_B_DONE>; + }; + + mdp_imgi@15020000 { + compatible = "mediatek,mt8183-mdp-imgi"; + mediatek,mdp-id = <0>; + reg = <0 0x15020000 0 0x1000>; + }; + + mdp_img2o@15020000 { + compatible = "mediatek,mt8183-mdp-exto"; + mediatek,mdp-id = <1>; + }; + + mdp_rsz0: mdp_rsz0@14003000 { + compatible = "mediatek,mt8183-mdp-rsz"; + mediatek,mdp-id = <0>; + reg = <0 0x14003000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp_rsz1: mdp_rsz1@14004000 { + compatible = "mediatek,mt8183-mdp-rsz"; + mediatek,mdp-id = <1>; + reg = <0 0x14004000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; + + mdp_wrot0: mdp_wrot0@14005000 { + compatible = "mediatek,mt8183-mdp-wrot"; + mediatek,mdp-id = <0>; + reg = <0 0x14005000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + mediatek,larb = <&larb0>; + }; + + mdp_path0_sout@14005000 { + compatible = "mediatek,mt8183-mdp-path"; + mediatek,mdp-id = <0>; + }; + + mdp_wdma: mdp_wdma@14006000 { + compatible = "mediatek,mt8183-mdp-wdma"; + mediatek,mdp-id = <0>; + reg = <0 0x14006000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu M4U_PORT_MDP_WDMA0>; + mediatek,larb = <&larb0>; + }; + + mdp_path1_sout@14006000 { + compatible = "mediatek,mt8183-mdp-path"; + mediatek,mdp-id = <1>; + }; + + mdp_ccorr: mdp_ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp-ccorr"; + mediatek,mdp-id = <0>; + reg = <0 0x1401c000 0 0x1000>; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + };