| Message ID | 1553613207-3988-2-git-send-email-vidyas@nvidia.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Tegra194 PCIe support | expand |
On Tue, 26 Mar 2019 20:43:18 +0530Vidya Sagar wrote: > > save pci_bus pointer created by PCIe sub-system's > pci_scan_root_bus_bridge() to be used by host controller drivers for post > processing. Tegra host controller driver needs it for the following > reasons > - to derive pci_host_bridge structure from pci_bus which is used to > configure iATU's outbound regions for different windows accesses > - to traverse and configure downstream hierarchy. One such case is, > configuring all immediate downstream devices to D0 state before transiting > link to L2 state. Saving pci_bus pointer seems the best method compared to > deriving it by other means. hmm, I submitted similar patch for another purpose last month, https://patchwork.kernel.org/patch/10830029/ then v3 weeks ago https://lkml.org/lkml/2019/3/18/375 And get Acks from Gustavo. But it seems that it isn't merged to dwc next branch in Lorenzo's tree Maybe Lorenzo have some idea of handling this case. Thanks
On 3/28/2019 12:48 PM, Jisheng Zhang wrote: > On Tue, 26 Mar 2019 20:43:18 +0530Vidya Sagar wrote: > >> >> save pci_bus pointer created by PCIe sub-system's >> pci_scan_root_bus_bridge() to be used by host controller drivers for post >> processing. Tegra host controller driver needs it for the following >> reasons >> - to derive pci_host_bridge structure from pci_bus which is used to >> configure iATU's outbound regions for different windows accesses >> - to traverse and configure downstream hierarchy. One such case is, >> configuring all immediate downstream devices to D0 state before transiting >> link to L2 state. Saving pci_bus pointer seems the best method compared to >> deriving it by other means. > > hmm, I submitted similar patch for another purpose last month, > > https://patchwork.kernel.org/patch/10830029/ > > then v3 weeks ago > > https://lkml.org/lkml/2019/3/18/375 > > And get Acks from Gustavo. But it seems that it isn't merged to dwc next > branch in Lorenzo's tree > > Maybe Lorenzo have some idea of handling this case. > > Thanks > Thanks for the info. I'll drop my patch once I see yours in dwc next branch. Thanks, Vidya Sagar
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 25087d3c9a82..15add3cf3945 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -494,6 +494,7 @@ int dw_pcie_host_init(struct pcie_port *pp) goto error; bus = bridge->bus; + pp->bus = bus; if (pp->ops->scan_bus) pp->ops->scan_bus(pp); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 377f4c0b52da..70007276bc93 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -175,6 +175,7 @@ struct pcie_port { struct resource *busn; int irq; const struct dw_pcie_host_ops *ops; + struct pci_bus *bus; int msi_irq; struct irq_domain *irq_domain; struct irq_domain *msi_domain;
save pci_bus pointer created by PCIe sub-system's pci_scan_root_bus_bridge() to be used by host controller drivers for post processing. Tegra host controller driver needs it for the following reasons - to derive pci_host_bridge structure from pci_bus which is used to configure iATU's outbound regions for different windows accesses - to traverse and configure downstream hierarchy. One such case is, configuring all immediate downstream devices to D0 state before transiting link to L2 state. Saving pci_bus pointer seems the best method compared to deriving it by other means. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- drivers/pci/controller/dwc/pcie-designware-host.c | 1 + drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 2 insertions(+)