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Thu, 25 Apr 2019 11:17:39 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id AE53731; Thu, 25 Apr 2019 09:17:33 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 91F4C1615; Thu, 25 Apr 2019 09:17:33 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 25 Apr 2019 11:17:33 +0200 Received: from localhost (10.201.23.25) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Apr 2019 11:17:32 +0200 From: Fabien Dessenne To: Ohad Ben-Cohen , Bjorn Andersson , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Jonathan Corbet , , , , , , Subject: [PATCH v2 3/6] dt-bindings: hwlock: update STM32 #hwlock-cells value Date: Thu, 25 Apr 2019 11:17:20 +0200 Message-ID: <1556183843-28033-4-git-send-email-fabien.dessenne@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> References: <1556183843-28033-1-git-send-email-fabien.dessenne@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.25] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-04-25_08:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190425_021746_702698_A7D2FB80 X-CRM114-Status: GOOD ( 16.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Benjamin Gaignard , Fabien Dessenne Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Use a value of 2, so users can share hwlocks. Signed-off-by: Fabien Dessenne Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt index adf4f000..60a3716 100644 --- a/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt +++ b/Documentation/devicetree/bindings/hwlock/st,stm32-hwspinlock.txt @@ -4,8 +4,8 @@ STM32 Hardware Spinlock Device Binding Required properties : - compatible : should be "st,stm32-hwspinlock". - reg : the register address of hwspinlock. -- #hwlock-cells : hwlock users only use the hwlock id to represent a specific - hwlock, so the number of cells should be <1> here. +- #hwlock-cells : should be <2> so the hwlock users use the hwlock id to + represent a specific hwlock and define its shared / exclusive attribute. - clock-names : Must contain "hsem". - clocks : Must contain a phandle entry for the clock in clock-names, see the common clock bindings. @@ -16,7 +16,7 @@ Please look at the generic hwlock binding for usage information for consumers, Example of hwlock provider: hwspinlock@4c000000 { compatible = "st,stm32-hwspinlock"; - #hwlock-cells = <1>; + #hwlock-cells = <2>; reg = <0x4c000000 0x400>; clocks = <&rcc HSEM>; clock-names = "hsem";