From patchwork Fri Apr 26 01:40:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 10917957 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3FCFE933 for ; Fri, 26 Apr 2019 01:48:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2B02228D27 for ; Fri, 26 Apr 2019 01:48:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1F3D228D80; Fri, 26 Apr 2019 01:48:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BE3DD28D27 for ; Fri, 26 Apr 2019 01:48:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=/7tnfDPNfgSN0/9whQGU2ZeCwBRW+w6E8Q/buteyp1o=; b=YIQ+SasxwbIvOl 0MiyQjS8rHSBkKaHOl4UGmGloLkMbgtGk+ThfUmkkMVsIvCEAaiV0IQ0C8Q5Mf+Nzadwjs4z7dRiv JM5g1GpQAH66DnPmyNI0U9RGr5QPtbB0xdgfmWHgIR279f9OglU0ToAlM81/pqzsjx+J9d5GYQEcd ExADQYnQHkMJJKGmqoCeZLyJ/cZJ/1PO4Xe1xIsVOIr0QF/xncqqf3PSfW8+fZqzaDuS2mKXUNh9w mMBlrjS1o00fPJHg1KOgUVB+e6CxKZ4KGUS9/8veodOqzRX/WX0dO2LwfysO8m6UycDTEmImwfxmn HO7hPVgyBJ32r84m9g1A==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hJpyE-0000zs-Qj; Fri, 26 Apr 2019 01:48:10 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hJpy4-0000t5-SB for linux-arm-kernel@lists.infradead.org; Fri, 26 Apr 2019 01:48:02 +0000 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id CA6F83F2F7962B52C67C; Fri, 26 Apr 2019 09:42:00 +0800 (CST) Received: from localhost.localdomain (10.67.212.132) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.439.0; Fri, 26 Apr 2019 09:41:53 +0800 From: Shaokun Zhang To: Subject: [PATCH 2/2] arm64: cacheinfo: Update cache_line_size detected from PPTT Date: Fri, 26 Apr 2019 09:40:21 +0800 Message-ID: <1556242821-5080-2-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1556242821-5080-1-git-send-email-zhangshaokun@hisilicon.com> References: <1556242821-5080-1-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.132] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190425_184801_086272_1AD944C4 X-CRM114-Status: GOOD ( 12.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , john.garry@huawei.com, Will Deacon , Shaokun Zhang , qiuzhenfa@hisilicon.com, guohanjun@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP cache_line_size is derived from CTR_EL0.CWG field and is called mostly for I/O device drivers. For HiSilicon certain plantform, like the Kunpeng920 server SoC, cache line sizes are different between L1/2 cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte, but CTR_EL0.CWG is misreporting using L1 cache line size. We shall correct the right value which is important for I/O performance. Let's update the cache line size if it is detected from PPTT information when it is larger than CTR_EL0.CWG reporting. Cc: Catalin Marinas Cc: Will Deacon Reported-by: Zhenfa Qiu Suggested-by: Catalin Marinas Signed-off-by: Shaokun Zhang --- arch/arm64/include/asm/cache.h | 6 +----- arch/arm64/kernel/cacheinfo.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h index 926434f413fa..f120d48b27ac 100644 --- a/arch/arm64/include/asm/cache.h +++ b/arch/arm64/include/asm/cache.h @@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void) #define __read_mostly __attribute__((__section__(".data..read_mostly"))) -static inline int cache_line_size(void) -{ - u32 cwg = cache_type_cwg(); - return cwg ? 4 << cwg : ARCH_DMA_MINALIGN; -} +extern int cache_line_size(void); /* * Read the effective value of CTR_EL0. diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 0bf0a835122f..0b26d53790a8 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -28,6 +28,21 @@ #define CLIDR_CTYPE(clidr, level) \ (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level)) +int cache_line_size(void) +{ + u32 cwg = cache_type_cwg(); + + if (cwg == 0) + return ARCH_DMA_MINALIGN; +#ifdef CONFIG_ACPI + /* compare cache line size detected from PPTT with CWG reporting */ + if (coherency_max_size > (4 << cwg)) + return coherency_max_size; +#endif + + return 4 << cwg; +} + static inline enum cache_type get_cache_type(int level) { u64 clidr;