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Mon, 13 May 2019 16:44:05 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3F7CB31; Mon, 13 May 2019 14:44:05 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas22.st.com [10.75.90.92]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1D99B2897; Mon, 13 May 2019 14:44:05 +0000 (GMT) Received: from SAFEX1HUBCAS24.st.com (10.75.90.95) by Safex1hubcas22.st.com (10.75.90.92) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 13 May 2019 16:44:05 +0200 Received: from localhost (10.201.23.97) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 13 May 2019 16:44:04 +0200 From: =?utf-8?q?Yannick_Fertr=C3=A9?= To: Yannick Fertre , Philippe Cornu , Benjamin Gaignard , Vincent Abriou , David Airlie , Daniel Vetter , Maxime Coquelin , Alexandre Torgue , , , , Subject: [PATCH v3 2/2] drm/stm: dsi: add support of an regulator Date: Mon, 13 May 2019 16:42:19 +0200 Message-ID: <1557758539-28748-3-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1557758539-28748-1-git-send-email-yannick.fertre@st.com> References: <1557758539-28748-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-05-13_07:, , signatures=0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190513_074410_261694_457E66A8 X-CRM114-Status: GOOD ( 17.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP Add support of an regulator for the phy part of the DSI controller. Signed-off-by: Yannick Fertré Acked-by: Philippe Cornu --- drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 53 +++++++++++++++++++++++++++++------ 1 file changed, 45 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c index 1bef73e..011e510 100644 --- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c +++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -76,6 +77,7 @@ struct dw_mipi_dsi_stm { u32 hw_version; int lane_min_kbps; int lane_max_kbps; + struct regulator *vdd_supply; }; static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) @@ -318,17 +320,31 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) return PTR_ERR(dsi->base); } + dsi->vdd_supply = devm_regulator_get_optional(dev, "phy-dsi"); + if (IS_ERR(dsi->vdd_supply)) { + ret = PTR_ERR(dsi->vdd_supply); + if (ret != -EPROBE_DEFER) + DRM_ERROR("Failed to request regulator: %d\n", ret); + return ret; + } + + ret = regulator_enable(dsi->vdd_supply); + if (ret) { + DRM_ERROR("Failed to enable regulator: %d\n", ret); + return ret; + } + dsi->pllref_clk = devm_clk_get(dev, "ref"); if (IS_ERR(dsi->pllref_clk)) { ret = PTR_ERR(dsi->pllref_clk); - dev_err(dev, "Unable to get pll reference clock: %d\n", ret); - return ret; + DRM_ERROR("Unable to get pll reference clock: %d\n", ret); + goto err_clk_get; } ret = clk_prepare_enable(dsi->pllref_clk); if (ret) { - dev_err(dev, "%s: Failed to enable pllref_clk\n", __func__); - return ret; + DRM_ERROR("Failed to enable pllref_clk\n"); + goto err_clk_get; } dw_mipi_dsi_stm_plat_data.base = dsi->base; @@ -339,19 +355,28 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev) dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data); if (IS_ERR(dsi->dsi)) { DRM_ERROR("Failed to initialize mipi dsi host\n"); - clk_disable_unprepare(dsi->pllref_clk); - return PTR_ERR(dsi->dsi); + ret = PTR_ERR(dsi->dsi); + goto err_dsi_probe; } return 0; + +err_dsi_probe: + clk_disable_unprepare(dsi->pllref_clk); +err_clk_get: + regulator_disable(dsi->vdd_supply); + + return ret; + } static int dw_mipi_dsi_stm_remove(struct platform_device *pdev) { struct dw_mipi_dsi_stm *dsi = platform_get_drvdata(pdev); - clk_disable_unprepare(dsi->pllref_clk); dw_mipi_dsi_remove(dsi->dsi); + clk_disable_unprepare(dsi->pllref_clk); + regulator_disable(dsi->vdd_supply); return 0; } @@ -363,6 +388,7 @@ static int __maybe_unused dw_mipi_dsi_stm_suspend(struct device *dev) DRM_DEBUG_DRIVER("\n"); clk_disable_unprepare(dsi->pllref_clk); + regulator_disable(dsi->vdd_supply); return 0; } @@ -370,10 +396,21 @@ static int __maybe_unused dw_mipi_dsi_stm_suspend(struct device *dev) static int __maybe_unused dw_mipi_dsi_stm_resume(struct device *dev) { struct dw_mipi_dsi_stm *dsi = dw_mipi_dsi_stm_plat_data.priv_data; + int ret; DRM_DEBUG_DRIVER("\n"); - clk_prepare_enable(dsi->pllref_clk); + ret = regulator_enable(dsi->vdd_supply); + if (ret) { + DRM_ERROR("Failed to enable regulator: %d\n", ret); + return ret; + } + + ret = clk_prepare_enable(dsi->pllref_clk); + if (ret) { + DRM_ERROR("Failed to enable pllref_clk\n"); + return ret; + } return 0; }