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Tue, 9 Jul 2019 09:19:29 +0200 (CEST) Received: from augenblix2.phytec.de ([172.16.21.122]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2019070909192926-309711 ; Tue, 9 Jul 2019 09:19:29 +0200 From: Stefan Riedmueller To: shawnguo@kernel.org, s.hauer@pengutronix.de, robh+dt@kernel.org, mark.rutland@arm.com Subject: [PATCH 08/10] ARM: dts: imx6ul: segin: Move ECSPI interface to board include file Date: Tue, 9 Jul 2019 09:19:25 +0200 Message-Id: <1562656767-273566-9-git-send-email-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1562656767-273566-1-git-send-email-s.riedmueller@phytec.de> References: <1562656767-273566-1-git-send-email-s.riedmueller@phytec.de> X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 09.07.2019 09:19:29, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 09.07.2019 09:19:29, Serialize complete at 09.07.2019 09:19:29 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPLMWRmVeSWpSXmKPExsWyRoCBS5fRQSXW4NUBHYv5R86xWjy86m+x aupOFotNj6+xWnT9WslscXnXHDaLpdcvMlk8uNjFYtG69wi7xd/tm1gsXmwRd+D2WDNvDaPH jrtLGD12zrrL7rFpVSebx+Yl9R4b3+1g8uj/a+DxeZNcAEcUl01Kak5mWWqRvl0CV8bEZ0dZ Cr4KVGz9cp61gbGHr4uRk0NCwETi0PRm1i5GLg4hgR2MEt2nL7BAOBcYJY4ubWUGqWITMJJY MK2RCcQWEYiUeLf9NztIEbPAHkaJadevM4IkhAWiJH4e/8YCYrMIqEi8mHQQyObg4BXwkLi2 jwdim5zEzXOdYDM5BTwljl78BWYLAZVcXjANbLGEQCOTxLXXWxghGoQkTi8+yzyBkW8BI8Mq RqHczOTs1KLMbL2CjMqS1GS9lNRNjMBAPTxR/dIOxr45HocYmTgYDzFKcDArifDuc1eOFeJN SaysSi3Kjy8qzUktPsQozcGiJM67gbckTEggPbEkNTs1tSC1CCbLxMEp1cBYdHyvxSH2s/+j tdX8drN6Byy5/0939ZYp5444zX4kJjjx6sMV1UzM/Aa1D1Q2TAmfo7f14t4/xwSTWBmLrpxJ nyT062jrim/BTyrPliU1lh67tb/Zy+bYoTfKaZE/JnckvZm/XsGw9Q7f10fCUw2m9sV83/9z dtu2/Kchftb6LJ+Kbjitfc9yR4mlOCPRUIu5qDgRAK9K5zVCAgAA X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190709_001937_706704_F225B6F9 X-CRM114-Status: GOOD ( 11.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, martyn.welch@collabora.com, linux-kernel@vger.kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP The ECSPI interface is available on the expansion connector of every PHYTEC phyBOARD-Segin. Move its definition to the board include file for better reuse. Signed-off-by: Stefan Riedmueller --- arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts | 14 -------------- arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts index c6ef13685a7c..32d90c67a6f2 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts +++ b/arch/arm/boot/dts/imx6ul-phytec-segin-ff-rdk-nand.dts @@ -28,9 +28,6 @@ }; &ecspi3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi3>; - cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -93,14 +90,3 @@ &usdhc1 { status = "okay"; }; - -&iomuxc { - pinctrl_ecspi3: ecspi3grp { - fsl,pins = < - MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 - MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 - MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 - MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 7cd24ec40c36..8d5f8dc6ad58 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -103,6 +103,13 @@ assigned-clock-rates = <786432000>; }; +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; @@ -225,6 +232,15 @@ >; }; + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x10b0 + MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x10b0 + MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x10b0 + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x10b0 + >; + }; + pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0