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Mon, 9 Sep 2019 03:39:39 +0000 Received: from AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::6ca2:ec08:2b37:8ab8]) by AM0PR04MB4481.eurprd04.prod.outlook.com ([fe80::6ca2:ec08:2b37:8ab8%6]) with mapi id 15.20.2241.018; Mon, 9 Sep 2019 03:39:39 +0000 From: Peng Fan To: "mturquette@baylibre.com" , "sboyd@kernel.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "festevam@gmail.com" Subject: [PATCH V3 2/4] clk: imx: clk-pll14xx: unbypass PLL by default Thread-Topic: [PATCH V3 2/4] clk: imx: clk-pll14xx: unbypass PLL by default Thread-Index: AQHVZsA1EtD+h9V9IEql7N7H+rcN+w== Date: Mon, 9 Sep 2019 03:39:39 +0000 Message-ID: <1568043491-20680-3-git-send-email-peng.fan@nxp.com> References: <1568043491-20680-1-git-send-email-peng.fan@nxp.com> In-Reply-To: <1568043491-20680-1-git-send-email-peng.fan@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR03CA0004.apcprd03.prod.outlook.com (2603:1096:203:2e::16) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) authentication-results: spf=none (sender IP is ) smtp.mailfrom=peng.fan@nxp.com; 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The PLL has two bypass control bit, BYPASS and EXT_BYPASS. we will expose EXT_BYPASS to clk driver for mux usage, and keep BYPASS inside pll14xx usage. The PLL has a restriction that when M/P change, need to RESET/BYPASS pll to avoid glitch, so we could not expose BYPASS. To make it easy for clk driver usage, unbypass PLL which does not hurt current function. Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by: Leonard Crestez Signed-off-by: Peng Fan --- V3: None V2: New patch drivers/clk/imx/clk-pll14xx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 656f48b002dd..7a815ec76aa5 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -368,6 +368,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, struct clk_pll14xx *pll; struct clk *clk; struct clk_init_data init; + u32 val; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) @@ -399,6 +400,10 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, pll->rate_table = pll_clk->rate_table; pll->rate_count = pll_clk->rate_count; + val = readl_relaxed(pll->base + GNRL_CTL); + val &= ~BYPASS_MASK; + writel_relaxed(val, pll->base + GNRL_CTL); + clk = clk_register(NULL, &pll->hw); if (IS_ERR(clk)) { pr_err("%s: failed to register pll %s %lu\n",