Message ID | 1572603166-24594-1-git-send-email-peng.fan@nxp.com (mailing list archive) |
---|---|
State | Mainlined |
Commit | 073a01e8d7c23b3efb59a3d4c20aa546f9ec29a9 |
Headers | show |
Series | clk: imx: clk-composite-8m: add lock to gate/mux | expand |
On 19-11-01 10:16:19, Peng Fan wrote: > From: Peng Fan <peng.fan@nxp.com> > > There is a lock to diviver in the composite driver, but that's not > enought. lock to gate/mux are also needed to provide exclusive access > to the register. > > Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") > Signed-off-by: Peng Fan <peng.fan@nxp.com> Looks good to me. Reviewed-by: Abel Vesa <abel.vesa@nxp.com> > --- > drivers/clk/imx/clk-composite-8m.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c > index e0f25983e80f..20f7c91c03d2 100644 > --- a/drivers/clk/imx/clk-composite-8m.c > +++ b/drivers/clk/imx/clk-composite-8m.c > @@ -142,6 +142,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, > mux->reg = reg; > mux->shift = PCG_PCS_SHIFT; > mux->mask = PCG_PCS_MASK; > + mux->lock = &imx_ccm_lock; > > div = kzalloc(sizeof(*div), GFP_KERNEL); > if (!div) > @@ -161,6 +162,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, > gate_hw = &gate->hw; > gate->reg = reg; > gate->bit_idx = PCG_CGC_SHIFT; > + gate->lock = &imx_ccm_lock; > > hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, > mux_hw, &clk_mux_ops, div_hw, > -- > 2.16.4 >
On Fri, Nov 01, 2019 at 10:16:19AM +0000, Peng Fan wrote: > From: Peng Fan <peng.fan@nxp.com> > > There is a lock to diviver in the composite driver, but that's not s/diviver/divider > enought. lock to gate/mux are also needed to provide exclusive access s/enought/enough > to the register. > > Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") > Signed-off-by: Peng Fan <peng.fan@nxp.com> Other than above typos, Acked-by: Shawn Guo <shawnguo@kernel.org> Stephen, I assume you will take it a fix. Otherwise, please let me know. Shawn > --- > drivers/clk/imx/clk-composite-8m.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c > index e0f25983e80f..20f7c91c03d2 100644 > --- a/drivers/clk/imx/clk-composite-8m.c > +++ b/drivers/clk/imx/clk-composite-8m.c > @@ -142,6 +142,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, > mux->reg = reg; > mux->shift = PCG_PCS_SHIFT; > mux->mask = PCG_PCS_MASK; > + mux->lock = &imx_ccm_lock; > > div = kzalloc(sizeof(*div), GFP_KERNEL); > if (!div) > @@ -161,6 +162,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, > gate_hw = &gate->hw; > gate->reg = reg; > gate->bit_idx = PCG_CGC_SHIFT; > + gate->lock = &imx_ccm_lock; > > hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, > mux_hw, &clk_mux_ops, div_hw, > -- > 2.16.4 >
On Tue, Dec 03, 2019 at 01:03:38AM -0800, Stephen Boyd wrote: > Quoting Shawn Guo (2019-12-02 00:19:49) > > On Fri, Nov 01, 2019 at 10:16:19AM +0000, Peng Fan wrote: > > > From: Peng Fan <peng.fan@nxp.com> > > > > > > There is a lock to diviver in the composite driver, but that's not > > > > s/diviver/divider > > > > > enought. lock to gate/mux are also needed to provide exclusive access > > > > s/enought/enough > > > > > to the register. > > > > > > Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") > > > Signed-off-by: Peng Fan <peng.fan@nxp.com> > > > > Other than above typos, > > > > Acked-by: Shawn Guo <shawnguo@kernel.org> > > > > Stephen, > > > > I assume you will take it a fix. Otherwise, please let me know. > > > > Is this a critical fix for this merge window? I'm not sure it is > important so I marked it as "awaiting upstream" and assumed you would > send it on up later. Okay. I queued it up. Shawn
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index e0f25983e80f..20f7c91c03d2 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -142,6 +142,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, mux->reg = reg; mux->shift = PCG_PCS_SHIFT; mux->mask = PCG_PCS_MASK; + mux->lock = &imx_ccm_lock; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) @@ -161,6 +162,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, gate_hw = &gate->hw; gate->reg = reg; gate->bit_idx = PCG_CGC_SHIFT; + gate->lock = &imx_ccm_lock; hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &clk_mux_ops, div_hw,