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Fri, 22 Nov 2019 10:48:20 +0000 Received: from AM0PR04MB5779.eurprd04.prod.outlook.com ([fe80::fd44:1b14:587c:9fde]) by AM0PR04MB5779.eurprd04.prod.outlook.com ([fe80::fd44:1b14:587c:9fde%7]) with mapi id 15.20.2474.019; Fri, 22 Nov 2019 10:48:20 +0000 From: Abel Vesa To: Aisheng Dong , Shawn Guo , Leonard Crestez , Stephen Boyd , Sascha Hauer , Jacky Bai Subject: [PATCH v2 10/11] clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based Thread-Topic: [PATCH v2 10/11] clk: imx: Rename the imx_clk_divider_gate to imply it's clk_hw based Thread-Index: AQHVoSJa60rJnfieYEWB/AveoN7W2Q== Date: Fri, 22 Nov 2019 10:48:19 +0000 Message-ID: <1574419679-3813-11-git-send-email-abel.vesa@nxp.com> References: <1574419679-3813-1-git-send-email-abel.vesa@nxp.com> In-Reply-To: <1574419679-3813-1-git-send-email-abel.vesa@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: AM0PR0402CA0020.eurprd04.prod.outlook.com (2603:10a6:208:15::33) To AM0PR04MB5779.eurprd04.prod.outlook.com (2603:10a6:208:131::23) x-originating-ip: [89.37.124.34] x-mailer: git-send-email 2.7.4 authentication-results: spf=none (sender IP is ) smtp.mailfrom=abel.vesa@nxp.com; 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H:AM0PR04MB5779.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: WyJCDvqKpE3vYso1lRiIEbq+nqDsymUMv712tuv7rhhV7XEULnKYrWdTv+UqEUsGcib+Ppo3LL1cMcOGokTxEcjrIflwoFV2Nn3R4kre6z+0xzB4MkMCkVV/fYGBk8rouPiUdUSTWX0hl7VFIRnCFSDiR0mPuXEl3LmiR+B8zAwh75gcD4bxl/F0MMM74NfjoRFcvolXc3x319OBOjb71Du4bZgTgaWGVqeerAVl+MDF4t9w5vWMcHs+bgKbZN4WIN7ljRX4y6FiiuXCamnXH/Tljw7IxVpdvWSBoYxVXkYWdxuA3czEYT/yz2+dcFy/nvg4yP7vzYHx6CJtZnlr57bMepdQ7h1omlKPufB6R7M8TSMBgV8sczlMdLo+d4WFLrzTaX/gtMAREX3sO7nX3rWG3IYhiEiTrFK+tg2VlpIfwl3j5kl1Vpk983Yg2dYd MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 740287b7-edf2-487b-acff-08d76f397cc5 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Nov 2019 10:48:19.5491 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 83ccdoIRkDHzG6zDtMz7l27XI35cui4VpjTD7WuIv90xtbZEZwgLJQsATXMk5dzLKwkx3q/L9KFHrltG9+bSCQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6961 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191122_024833_909550_844457B6 X-CRM114-Status: GOOD ( 13.27 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [40.107.6.66 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peng Fan , Abel Vesa , Linux Kernel Mailing List , dl-linux-imx , "linux-clk@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Renaming the imx_clk_divider_gate register function to imx_clk_hw_divider_gate to be more obvious it is clk_hw based. Signed-off-by: Abel Vesa Reviewed-by: Peng Fan --- drivers/clk/imx/clk-divider-gate.c | 2 +- drivers/clk/imx/clk-imx7ulp.c | 8 ++++---- drivers/clk/imx/clk.h | 2 +- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/imx/clk-divider-gate.c b/drivers/clk/imx/clk-divider-gate.c index 2a8352a..905aee5 100644 --- a/drivers/clk/imx/clk-divider-gate.c +++ b/drivers/clk/imx/clk-divider-gate.c @@ -173,7 +173,7 @@ static const struct clk_ops clk_divider_gate_ops = { * default as our HW is. Besides that it supports only CLK_DIVIDER_READ_ONLY * flag which can be specified by user flexibly. */ -struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name, +struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, diff --git a/drivers/clk/imx/clk-imx7ulp.c b/drivers/clk/imx/clk-imx7ulp.c index 314f9c2..8657e5f 100644 --- a/drivers/clk/imx/clk-imx7ulp.c +++ b/drivers/clk/imx/clk-imx7ulp.c @@ -111,7 +111,7 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) clks[IMX7ULP_CLK_APLL_SEL] = imx_clk_hw_mux_flags("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); clks[IMX7ULP_CLK_SPLL_SEL] = imx_clk_hw_mux_flags("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE); - clks[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock); + clks[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock); /* scs/ddr/nic select different clock source requires that clock to be enabled first */ clks[IMX7ULP_CLK_SYS_SEL] = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels)); @@ -122,7 +122,7 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) clks[IMX7ULP_CLK_CORE_DIV] = imx_clk_hw_divider_flags("divcore", "scs_sel", base + 0x14, 16, 4, CLK_SET_RATE_PARENT); clks[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT); - clks[IMX7ULP_CLK_DDR_DIV] = imx_clk_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3, + clks[IMX7ULP_CLK_DDR_DIV] = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3, 0, ulp_div_table, &imx_ccm_lock); clks[IMX7ULP_CLK_NIC0_DIV] = imx_clk_hw_divider_flags("nic0_clk", "nic_sel", base + 0x40, 24, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL); @@ -131,9 +131,9 @@ static void __init imx7ulp_clk_scg1_init(struct device_node *np) clks[IMX7ULP_CLK_GPU_DIV] = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4); - clks[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3, + clks[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_hw_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3, CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock); - clks[IMX7ULP_CLK_FIRC_BUS_CLK] = imx_clk_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, 3, + clks[IMX7ULP_CLK_FIRC_BUS_CLK] = imx_clk_hw_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, 3, CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock); imx_check_clk_hws(clks, clk_data->num); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index c9f626e..a1cb2d5 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -468,7 +468,7 @@ struct clk *imx8m_clk_composite_flags(const char *name, #define imx8m_clk_composite_critical(name, parent_names, reg) \ __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL) -struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name, +struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags, const struct clk_div_table *table, spinlock_t *lock);