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Wed, 18 Dec 2019 00:41:00 -0800 Received: from MTKMBS02N1.mediatek.inc (172.21.101.77) by MTKMBS62N1.mediatek.inc (172.29.193.41) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Dec 2019 00:31:20 -0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Dec 2019 16:30:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 18 Dec 2019 16:30:30 +0800 From: Weiyi Lu To: Nicolas Boichat , Matthias Brugger , Rob Herring , Sascha Hauer Subject: [PATCH v10 07/12] soc: mediatek: Remove infracfg misc driver support Date: Wed, 18 Dec 2019 16:30:43 +0800 Message-ID: <1576657848-14711-8-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1576657848-14711-1-git-send-email-weiyi.lu@mediatek.com> References: <1576657848-14711-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191218_004105_235411_DF26B296 X-CRM114-Status: GOOD ( 13.66 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.2 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: James Liao , Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Fan Chen , linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org In previous patches, we introduce scpsys-ext driver that covers the functions which infracfg misc driver provided. And then replace bus_prot_mask with bp_table of all compatibles. Now, we're going to remove infracfg misc drvier which is no longer being used. Signed-off-by: Weiyi Lu --- drivers/soc/mediatek/Kconfig | 10 ----- drivers/soc/mediatek/Makefile | 3 +- drivers/soc/mediatek/mtk-infracfg.c | 79 ----------------------------------- include/linux/soc/mediatek/infracfg.h | 39 ----------------- 4 files changed, 1 insertion(+), 130 deletions(-) delete mode 100644 drivers/soc/mediatek/mtk-infracfg.c delete mode 100644 include/linux/soc/mediatek/infracfg.h diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig index 2114b56..f837b3c 100644 --- a/drivers/soc/mediatek/Kconfig +++ b/drivers/soc/mediatek/Kconfig @@ -10,21 +10,12 @@ config MTK_CMDQ depends on ARCH_MEDIATEK || COMPILE_TEST select MAILBOX select MTK_CMDQ_MBOX - select MTK_INFRACFG help Say yes here to add support for the MediaTek Command Queue (CMDQ) driver. The CMDQ is used to help read/write registers with critical time limitation, such as updating display configuration during the vblank. -config MTK_INFRACFG - bool "MediaTek INFRACFG Support" - select REGMAP - help - Say yes here to add support for the MediaTek INFRACFG controller. The - INFRACFG controller contains various infrastructure registers not - directly associated to any device. - config MTK_PMIC_WRAP tristate "MediaTek PMIC Wrapper Support" depends on RESET_CONTROLLER @@ -38,7 +29,6 @@ config MTK_SCPSYS bool "MediaTek SCPSYS Support" default ARCH_MEDIATEK select REGMAP - select MTK_INFRACFG select PM_GENERIC_DOMAINS if PM help Say yes here to add support for the MediaTek SCPSYS power domain diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index b442be9..7bf7e88 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o -obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o mtk-scpsys-ext.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o -obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o +obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o mtk-scpsys-ext.o diff --git a/drivers/soc/mediatek/mtk-infracfg.c b/drivers/soc/mediatek/mtk-infracfg.c deleted file mode 100644 index 341c7ac..0000000 --- a/drivers/soc/mediatek/mtk-infracfg.c +++ /dev/null @@ -1,79 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2015 Pengutronix, Sascha Hauer - */ - -#include -#include -#include -#include -#include - -#define MTK_POLL_DELAY_US 10 -#define MTK_POLL_TIMEOUT (jiffies_to_usecs(HZ)) - -#define INFRA_TOPAXI_PROTECTEN 0x0220 -#define INFRA_TOPAXI_PROTECTSTA1 0x0228 -#define INFRA_TOPAXI_PROTECTEN_SET 0x0260 -#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264 - -/** - * mtk_infracfg_set_bus_protection - enable bus protection - * @regmap: The infracfg regmap - * @mask: The mask containing the protection bits to be enabled. - * @reg_update: The boolean flag determines to set the protection bits - * by regmap_update_bits with enable register(PROTECTEN) or - * by regmap_write with set register(PROTECTEN_SET). - * - * This function enables the bus protection bits for disabled power - * domains so that the system does not hang when some unit accesses the - * bus while in power down. - */ -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update) -{ - u32 val; - int ret; - - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, - mask); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); - - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, (val & mask) == mask, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - - return ret; -} - -/** - * mtk_infracfg_clear_bus_protection - disable bus protection - * @regmap: The infracfg regmap - * @mask: The mask containing the protection bits to be disabled. - * @reg_update: The boolean flag determines to clear the protection bits - * by regmap_update_bits with enable register(PROTECTEN) or - * by regmap_write with clear register(PROTECTEN_CLR). - * - * This function disables the bus protection bits previously enabled with - * mtk_infracfg_set_bus_protection. - */ - -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update) -{ - int ret; - u32 val; - - if (reg_update) - regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); - else - regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); - - ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, - val, !(val & mask), - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); - - return ret; -} diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h deleted file mode 100644 index fd25f01..0000000 --- a/include/linux/soc/mediatek/infracfg.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __SOC_MEDIATEK_INFRACFG_H -#define __SOC_MEDIATEK_INFRACFG_H - -#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0) -#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1) -#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2) -#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6) -#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9) -#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11) -#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12) -#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13) -#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14) -#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15) -#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16) -#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17) -#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18) -#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19) -#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20) -#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21) -#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22) -#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23) - -#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1) -#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2) -#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8) - -#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17)) -#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25)) -#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \ - BIT(28)) -#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \ - BIT(7) | BIT(8)) - -int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update); -int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, - bool reg_update); -#endif /* __SOC_MEDIATEK_INFRACFG_H */