| Message ID | 1581743758-4475-7-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add missing UART DCE/DTE pins macro defines | expand |
On Sat, Feb 15, 2020 at 01:15:57PM +0800, Anson Huang wrote: > Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this > is to distinguish the DCE/DTE functions. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
diff --git a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts index 28563f2..61c7e72 100644 --- a/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts @@ -384,15 +384,15 @@ pinctrl_uart1: uart1grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX 0x1b0b1 >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 - MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX 0x1b0b1 >; };
Use new pin names containing DCE/DTE for UART RX/TX/RTS/CTS pins, this is to distinguish the DCE/DTE functions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- arch/arm/boot/dts/imx6sx-softing-vining-2000.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)