| Message ID | 1582510060-12272-1-git-send-email-Anson.Huang@nxp.com (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 80b06c5cae5487f590988fd296be36ecd97ede2a |
| Headers | show |
| Series | [V2] arm64: dts: imx8mn: Adjust 1.2GHz OPP voltage to OD mode | expand |
On Mon, Feb 24, 2020 at 10:07:40AM +0800, Anson Huang wrote: > According to latest datasheet Rev.0, 10/2019, there is restriction > as below: > > "If VDD_SOC/GPU/DDR = 0.95V, then VDD_ARM must be >= 0.95V." > > As by default SoC is running at OD mode(VDD_SOC = 0.95V), so > VDD_ARM 1.2GHz OPP's voltage should be increased to 0.95V. > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Applied, thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index c98a376..f277572 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -116,7 +116,7 @@ opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <850000>; + opp-microvolt = <950000>; opp-supported-hw = <0xb00>, <0x7>; clock-latency-ns = <150000>; opp-suspend;
According to latest datasheet Rev.0, 10/2019, there is restriction as below: "If VDD_SOC/GPU/DDR = 0.95V, then VDD_ARM must be >= 0.95V." As by default SoC is running at OD mode(VDD_SOC = 0.95V), so VDD_ARM 1.2GHz OPP's voltage should be increased to 0.95V. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> --- Changes since V1: - Move the OPP change from board dts for soc dtsi. --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)