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Fri, 24 Apr 2020 04:11:46 -0700 (PDT) From: Sumit Garg To: linux-arm-kernel@lists.infradead.org Subject: [RFC Patch v1 3/4] irqchip/gic-v3: Enable arch specific IPI as pseudo NMI Date: Fri, 24 Apr 2020 16:39:13 +0530 Message-Id: <1587726554-32018-4-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1587726554-32018-1-git-send-email-sumit.garg@linaro.org> References: <1587726554-32018-1-git-send-email-sumit.garg@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200424_041149_302844_7E0E1B5A X-CRM114-Status: GOOD ( 12.05 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on bombadil.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:541 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sumit Garg , daniel.thompson@linaro.org, jason@lakedaemon.net, catalin.marinas@arm.com, jason.wessel@windriver.com, dianders@chromium.org, linux-kernel@vger.kernel.org, maz@kernel.org, kgdb-bugreport@lists.sourceforge.net, tglx@linutronix.de, will@kernel.org, julien.thierry.kdev@gmail.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add support to mark arch specific IPI as pseudo NMI. Currently its used to allows arm64 specific IPI_CALL_NMI_FUNC to be marked as pseudo NMI. Signed-off-by: Sumit Garg --- arch/arm64/kernel/smp.c | 5 +++++ drivers/irqchip/irq-gic-v3.c | 14 ++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index 42fe7bb..27c8ee1 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -802,6 +802,11 @@ static const char *ipi_types[NR_IPI] __tracepoint_string = { S(IPI_CALL_NMI_FUNC, "NMI function call interrupts"), }; +int arch_get_ipinr_nmi(void) +{ + return IPI_CALL_NMI_FUNC; +} + static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) { trace_ipi_raise(target, ipi_types[ipinr]); diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index be361bf..a3d2cf3 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1048,6 +1048,11 @@ static int gic_dist_supports_lpis(void) !gicv3_nolpi); } +int __weak arch_get_ipinr_nmi(void) +{ + return -1; +} + static void gic_cpu_init(void) { void __iomem *rbase; @@ -1072,6 +1077,15 @@ static void gic_cpu_init(void) gic_cpu_config(rbase, gic_data.ppi_nr + 16, gic_redist_wait_for_rwp); + if (gic_supports_nmi()) { + int ipinr; + + ipinr = arch_get_ipinr_nmi(); + if (ipinr >= 0 && ipinr < 16) + writeb_relaxed(GICD_INT_NMI_PRI, + rbase + GICD_IPRIORITYR + ipinr); + } + /* initialise system registers */ gic_cpu_sys_reg_init(); }