| Message ID | 1588652200-12341-3-git-send-email-zhangshaokun@hisilicon.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/3] arm64: perf: Add support caps in sysfs | expand |
Hi Will, On 2020/5/5 12:16, Shaokun Zhang wrote: > When PMU event ID is equal or greater than 0x4000, it will be reduced > by 0x4000 and it is not the raw number in the sysfs. Let's correct it > and obtain the right event ID. > > Before this patch: > cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed > event=0x001 > After this patch: > cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed > event=0x4001 > > Cc: Will Deacon <will@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> > --- > arch/arm64/kernel/perf_event.c | 13 ++++++++----- > 1 file changed, 8 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c > index 32c87cd48cbe..bd73e7f0e652 100644 > --- a/arch/arm64/kernel/perf_event.c > +++ b/arch/arm64/kernel/perf_event.c > @@ -155,7 +155,7 @@ armv8pmu_events_sysfs_show(struct device *dev, > > pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); > > - return sprintf(page, "event=0x%03llx\n", pmu_attr->id); > + return sprintf(page, "event=0x%04llx\n", pmu_attr->id); > } > > #define ARMV8_EVENT_ATTR(name, config) \ > @@ -263,10 +263,13 @@ armv8pmu_event_attr_is_visible(struct kobject *kobj, > test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap)) > return attr->mode; > > - pmu_attr->id -= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE; > - if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS && > - test_bit(pmu_attr->id, cpu_pmu->pmceid_ext_bitmap)) > - return attr->mode; > + if (pmu_attr->id > ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) { Apologies that this shall be: if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) { Thanks, Shaokun > + u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE; > + > + if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS && test_bit(id, > + cpu_pmu->pmceid_ext_bitmap)) > + return attr->mode; > + } > > return 0; > } >
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 32c87cd48cbe..bd73e7f0e652 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -155,7 +155,7 @@ armv8pmu_events_sysfs_show(struct device *dev, pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); - return sprintf(page, "event=0x%03llx\n", pmu_attr->id); + return sprintf(page, "event=0x%04llx\n", pmu_attr->id); } #define ARMV8_EVENT_ATTR(name, config) \ @@ -263,10 +263,13 @@ armv8pmu_event_attr_is_visible(struct kobject *kobj, test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap)) return attr->mode; - pmu_attr->id -= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE; - if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS && - test_bit(pmu_attr->id, cpu_pmu->pmceid_ext_bitmap)) - return attr->mode; + if (pmu_attr->id > ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) { + u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE; + + if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS && test_bit(id, + cpu_pmu->pmceid_ext_bitmap)) + return attr->mode; + } return 0; }
When PMU event ID is equal or greater than 0x4000, it will be reduced by 0x4000 and it is not the raw number in the sysfs. Let's correct it and obtain the right event ID. Before this patch: cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed event=0x001 After this patch: cat /sys/bus/event_source/devices/armv8_pmuv3_0/events/sample_feed event=0x4001 Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> --- arch/arm64/kernel/perf_event.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)