| Message ID | 1592905621-9689-1-git-send-email-abel.vesa@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RESEND] arm64: dts: imx8m: Add NOC nodes | expand |
Hi Abel, On 6/23/20 12:47, Abel Vesa wrote: > From: Leonard Crestez <leonard.crestez@nxp.com> > > Add nodes for the main interconnect of the imx8m series chips. > > These nodes are bound to by devfreq and interconnect drivers. > > Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com> > Tested-by: Martin Kepplinger <martin.kepplinger@puri.sm> > --- > > This is part of the following patchset: > > https://www.spinics.net/lists/arm-kernel/msg797026.html Nit: Looks like the previous version is also including the dt-bindings headers, but this part is missing here? In any case: Acked-by: Georgi Djakov <georgi.djakov@linaro.org> > > All the patches are already in except this one. > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 23 +++++++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 23 +++++++++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++ > 3 files changed, 69 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index c6bf8ba..00b96da 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -869,6 +869,29 @@ > > }; > > + noc: interconnect@32700000 { > + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; > + reg = <0x32700000 0x100000>; > + clocks = <&clk IMX8MM_CLK_NOC>; > + fsl,ddrc = <&ddrc>; > + #interconnect-cells = <1>; > + operating-points-v2 = <&noc_opp_table>; > + > + noc_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-150M { > + opp-hz = /bits/ 64 <150000000>; > + }; > + opp-375M { > + opp-hz = /bits/ 64 <375000000>; > + }; > + opp-750M { > + opp-hz = /bits/ 64 <750000000>; > + }; > + }; > + }; > + > aips4: bus@32c00000 { > compatible = "fsl,aips-bus", "simple-bus"; > reg = <0x32c00000 0x400000>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index 9a4b65a..656fa9b 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -756,6 +756,29 @@ > > }; > > + noc: interconnect@32700000 { > + compatible = "fsl,imx8mn-noc", "fsl,imx8m-noc"; > + reg = <0x32700000 0x100000>; > + clocks = <&clk IMX8MN_CLK_NOC>; > + fsl,ddrc = <&ddrc>; > + #interconnect-cells = <1>; > + operating-points-v2 = <&noc_opp_table>; > + > + noc_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-100M { > + opp-hz = /bits/ 64 <100000000>; > + }; > + opp-600M { > + opp-hz = /bits/ 64 <600000000>; > + }; > + opp-800M { > + opp-hz = /bits/ 64 <800000000>; > + }; > + }; > + }; > + > aips4: bus@32c00000 { > compatible = "fsl,aips-bus", "simple-bus"; > reg = <0x32c00000 0x400000>; > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 54bed64..6c24ec1 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -1037,6 +1037,29 @@ > }; > }; > > + noc: interconnect@32700000 { > + compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; > + reg = <0x32700000 0x100000>; > + clocks = <&clk IMX8MQ_CLK_NOC>; > + fsl,ddrc = <&ddrc>; > + #interconnect-cells = <1>; > + operating-points-v2 = <&noc_opp_table>; > + > + noc_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-133M { > + opp-hz = /bits/ 64 <133333333>; > + }; > + opp-400M { > + opp-hz = /bits/ 64 <400000000>; > + }; > + opp-800M { > + opp-hz = /bits/ 64 <800000000>; > + }; > + }; > + }; > + > bus@32c00000 { /* AIPS4 */ > compatible = "fsl,aips-bus", "simple-bus"; > reg = <0x32c00000 0x400000>; >
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c6bf8ba..00b96da 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -869,6 +869,29 @@ }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + fsl,ddrc = <&ddrc>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150M { + opp-hz = /bits/ 64 <150000000>; + }; + opp-375M { + opp-hz = /bits/ 64 <375000000>; + }; + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 9a4b65a..656fa9b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -756,6 +756,29 @@ }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mn-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MN_CLK_NOC>; + fsl,ddrc = <&ddrc>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + opp-600M { + opp-hz = /bits/ 64 <600000000>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 54bed64..6c24ec1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1037,6 +1037,29 @@ }; }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MQ_CLK_NOC>; + fsl,ddrc = <&ddrc>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133M { + opp-hz = /bits/ 64 <133333333>; + }; + opp-400M { + opp-hz = /bits/ 64 <400000000>; + }; + opp-800M { + opp-hz = /bits/ 64 <800000000>; + }; + }; + }; + bus@32c00000 { /* AIPS4 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>;