| Message ID | 1593694630-26604-8-git-send-email-hanks.chen@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v7,1/7] pinctrl: mediatek: update pinmux definitions for mt6779 | expand |
On 02/07/2020 14:57, Hanks Chen wrote: > Add MT6779 UART0 clock support. > > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") > Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> > Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> > --- > drivers/clk/mediatek/clk-mt6779.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c > index 9766ccc..6e0d3a1 100644 > --- a/drivers/clk/mediatek/clk-mt6779.c > +++ b/drivers/clk/mediatek/clk-mt6779.c > @@ -919,6 +919,8 @@ > "pwm_sel", 19), > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", > "pwm_sel", 21), > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", > + "uart_sel", 22), > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", > "uart_sel", 23), > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2", >
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 9766ccc..6e0d3a1 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -919,6 +919,8 @@ "pwm_sel", 19), GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm", "pwm_sel", 21), + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0", + "uart_sel", 22), GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1", "uart_sel", 23), GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
Add MT6779 UART0 clock support. Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Wendell Lin <wendell.lin@mediatek.com> Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> --- drivers/clk/mediatek/clk-mt6779.c | 2 ++ 1 file changed, 2 insertions(+)