From patchwork Wed Aug 19 08:06:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "liuqi (BA)" X-Patchwork-Id: 11723225 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 654E615E4 for ; Wed, 19 Aug 2020 08:09:45 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3DE562067C for ; Wed, 19 Aug 2020 08:09:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="F180+xg2" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3DE562067C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=xlE/VwBvFU5fmG8VapYf5KqxIzi5+pcOFcTib6xxYkE=; b=F180+xg2VYWfjo7J+spWDKYae1 7pAijMNfnVRQZT/D0L5cowPQuQ0ICZsueMurQiL9dCRb8LZUEAXHZXe0vJciomny9CprVckOnyyHl 4vdAwk2A9BqbpW8W3TkPtNDzk8Z3a8rshcqS0dQe8Ky3Bj9Hrm3YahbHDvCKHhSoA4igci5xopbpr T7PsBMMLbmvgIe7Ul1pgdkXIGREnjq+C3XkGemq72mqfgCqVHEGUlCVR2A1/qZMJtvDtyhit8/xLI UF8B0IbLPsS7VDjn6QxY/JdMgpw2ftnqG/sEm8FwRimLFv2UdCTG7Jr4y87eERHNVdxyUwEVUmPon os5iT6fA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1k8J8X-0006hX-WD; Wed, 19 Aug 2020 08:07:58 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1k8J8V-0006gF-3P for linux-arm-kernel@lists.infradead.org; Wed, 19 Aug 2020 08:07:56 +0000 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6F9F573DCBE657F3034D; Wed, 19 Aug 2020 16:07:40 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Wed, 19 Aug 2020 16:07:33 +0800 From: Qi Liu To: , , , Subject: [RFC PATCH v2] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM Date: Wed, 19 Aug 2020 16:06:37 +0800 Message-ID: <1597824397-29894-1-git-send-email-liuqi115@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200819_040755_402018_9091F0D5 X-CRM114-Status: GOOD ( 14.37 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.35 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.35 listed in wl.mailspike.net] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org When too much trace information is generated on-chip, the ETM will overflow, and cause data loss. This is a common phenomenon on ETM devices. But sometimes we do not want to lose performance trace data, so we suppress the speed of instructions sent from CPU core to ETM to avoid the overflow of ETM. Signed-off-by: Qi Liu --- Changes since v1: - ETM on HiSilicon Hip09 platform supports backpressure, so does not need to modify core commit. drivers/hwtracing/coresight/coresight-etm4x.c | 43 +++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) -- 2.8.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 7797a57..7641f89 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -43,6 +43,10 @@ MODULE_PARM_DESC(boot_enable, "Enable tracing on boot"); #define PARAM_PM_SAVE_NEVER 1 /* never save any state */ #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */ +#define CORE_COMMIT_CLEAR 0x3000 +#define CORE_COMMIT_SHIFT 12 +#define HISI_ETM_AMBA_ID_V1 0x000b6d01 + static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE; module_param(pm_save_enable, int, 0444); MODULE_PARM_DESC(pm_save_enable, @@ -104,11 +108,40 @@ struct etm4_enable_arg { int rc; }; +static void etm4_cpu_actlr1_cfg(void *info) +{ + struct etm4_enable_arg *arg = (struct etm4_enable_arg *)info; + u64 val; + + asm volatile("mrs %0,s3_1_c15_c2_5" : "=r"(val)); + val &= ~CORE_COMMIT_CLEAR; + val |= arg->rc << CORE_COMMIT_SHIFT; + asm volatile("msr s3_1_c15_c2_5,%0" : : "r"(val)); +} + +static void etm4_config_core_commit(int cpu, int val) +{ + struct etm4_enable_arg arg = {0}; + + arg.rc = val; + smp_call_function_single(cpu, etm4_cpu_actlr1_cfg, &arg, 1); +} + static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; + struct amba_device *adev; struct etmv4_config *config = &drvdata->config; struct device *etm_dev = &drvdata->csdev->dev; + struct device *dev = drvdata->csdev->dev.parent; + + adev = container_of(dev, struct amba_device, dev); + /* + * If ETM device is HiSilicon ETM device, reduce the + * core-commit to avoid ETM overflow. + */ + if (adev->periphid == HISI_ETM_AMBA_ID_V1) + etm4_config_core_commit(drvdata->cpu, 1); CS_UNLOCK(drvdata->base); @@ -472,10 +505,20 @@ static void etm4_disable_hw(void *info) { u32 control; struct etmv4_drvdata *drvdata = info; + struct device *dev = drvdata->csdev->dev.parent; struct etmv4_config *config = &drvdata->config; struct device *etm_dev = &drvdata->csdev->dev; + struct amba_device *adev; int i; + adev = container_of(dev, struct amba_device, dev); + /* + * If ETM device is HiSilicon ETM device, resume the + * core-commit after ETM trace is complete. + */ + if (adev->periphid == HISI_ETM_AMBA_ID_V1) + etm4_config_core_commit(drvdata->cpu, 0); + CS_UNLOCK(drvdata->base); if (!drvdata->skip_power_up) {