From patchwork Thu Sep 3 11:37:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "liuqi (BA)" X-Patchwork-Id: 11753419 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id B5DE113B1 for ; Thu, 3 Sep 2020 11:40:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 896C72071B for ; Thu, 3 Sep 2020 11:40:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="N4ITBzpr" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 896C72071B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=mQ21xlds1PnBuSxH7ThOF2EmCVidNCvJolHlSLDaO/8=; b=N4ITBzprKxkLqn4XkxmJmiSyJH oYZWcXhzhRkclXsTWxZKJsigv42//L9V2l+/S6FFBckzYx4+HOGJY5QYAPEkTrNrWQ1VeGQjQ2sIW 7vGCBgYuxOP+Imuj15qJcnhjPgqMySjf4bfCoPJLQxJYJiY5xB20/hwwf6iw7wVKudzBhRy0d7ny2 5pCyuH9OU5Ak3HFlcN2KN7IcnpK1g49Lo7Fmut2fknWjtEc2ZPi0HOaBRQOwoxUNYN7/cFLhNWWuB On6fT80wUfEYR3JmmXDY5ZeTvD70HfXyxvzZqlg4WQSVSGr0Isxo/S1z6D7JTUdHq9kPWpWi0A+mk PZUpenew==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kDnZh-0008UL-24; Thu, 03 Sep 2020 11:38:41 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kDnZd-0008Sm-FG for linux-arm-kernel@lists.infradead.org; Thu, 03 Sep 2020 11:38:38 +0000 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 034C48D1C9FB848B0584; Thu, 3 Sep 2020 19:38:26 +0800 (CST) Received: from localhost.localdomain (10.67.165.24) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Thu, 3 Sep 2020 19:38:17 +0800 From: Qi Liu To: , , Subject: [PATCH] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM Date: Thu, 3 Sep 2020 19:37:14 +0800 Message-ID: <1599133034-38747-1-git-send-email-liuqi115@huawei.com> X-Mailer: git-send-email 2.8.1 MIME-Version: 1.0 X-Originating-IP: [10.67.165.24] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200903_073838_019390_EDF27C69 X-CRM114-Status: GOOD ( 13.46 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.35 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.35 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linuxarm@huawei.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org The ETM device can't keep up with the core pipeline when cpu core is at full speed. This may cause overflow within core and its ETM. This is a common phenomenon on ETM devices. On HiSilicon Hip08 platform, a specific feature is added to set core pipeline. So commit rate can be reduced manually to avoid ETM overflow. Signed-off-by: Qi Liu --- link of the RFC patch: https://lore.kernel.org/linux-arm-kernel/1597824397-29894-1-git-send-email-liuqi115@huawei.com/ drivers/hwtracing/coresight/coresight-etm4x.c | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) -- 2.8.1 diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c index 7bcac88..5833be1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.c +++ b/drivers/hwtracing/coresight/coresight-etm4x.c @@ -45,6 +45,10 @@ static int etm4_set_event_filters(struct etmv4_drvdata *drvdata, static enum cpuhp_state hp_online; +#define HISI_HIP08_CORE_COMMIT_CLEAR 0x3000 +#define HISI_HIP08_CORE_COMMIT_SHIFT 12 +#define HISI_HIP08_ETM_ID 0x000b6d01 + static void etm4_os_unlock(struct etmv4_drvdata *drvdata) { /* Writing any value to ETMOSLAR unlocks the trace registers */ @@ -84,12 +88,38 @@ struct etm4_enable_arg { int rc; }; +static void etm4_hisi_config_core_commit(int flag) +{ + u64 val; + + asm volatile("mrs %0,s3_1_c15_c2_5" : "=r"(val)); + val &= ~HISI_HIP08_CORE_COMMIT_CLEAR; + val |= flag << HISI_HIP08_CORE_COMMIT_SHIFT; + asm volatile("msr s3_1_c15_c2_5,%0" : : "r"(val)); +} + +static void etm4_enable_arch_specific(struct etmv4_drvdata *drvdata) +{ + struct device *dev = drvdata->csdev->dev.parent; + struct amba_device *adev; + + adev = container_of(dev, struct amba_device, dev); + + /* + * If ETM device is HiSilicon ETM device, reduce the + * core-commit to avoid ETM overflow. + */ + if (adev->periphid == HISI_HIP08_ETM_ID) + etm4_hisi_config_core_commit(1); +} + static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; struct etmv4_config *config = &drvdata->config; struct device *etm_dev = &drvdata->csdev->dev; + etm4_enable_arch_specific(drvdata); CS_UNLOCK(drvdata->base); etm4_os_unlock(drvdata); @@ -436,11 +466,27 @@ static int etm4_enable(struct coresight_device *csdev, return ret; } +static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) +{ + struct device *dev = drvdata->csdev->dev.parent; + struct amba_device *adev; + + adev = container_of(dev, struct amba_device, dev); + + /* + * If ETM device is HiSilicon ETM device, resume the + * core-commit after ETM trace is complete. + */ + if (adev->periphid == HISI_HIP08_ETM_ID) + etm4_hisi_config_core_commit(0); +} + static void etm4_disable_hw(void *info) { u32 control; struct etmv4_drvdata *drvdata = info; + etm4_disable_arch_specific(drvdata); CS_UNLOCK(drvdata->base); /* power can be removed from the trace unit now */