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Thu, 03 Sep 2020 05:05:55 -0700 (PDT) From: Sumit Garg To: maz@kernel.org, catalin.marinas@arm.com, will@kernel.org Subject: [PATCH v3 2/4] irqchip/gic-v3: Enable support for SGIs to act as NMIs Date: Thu, 3 Sep 2020 17:35:10 +0530 Message-Id: <1599134712-30923-3-git-send-email-sumit.garg@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599134712-30923-1-git-send-email-sumit.garg@linaro.org> References: <1599134712-30923-1-git-send-email-sumit.garg@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200903_080558_508168_B315ACB1 X-CRM114-Status: GOOD ( 15.43 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:443 listed in] [list.dnswl.org] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sumit Garg , daniel.thompson@linaro.org, jason@lakedaemon.net, kgdb-bugreport@lists.sourceforge.net, dianders@chromium.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jason.wessel@windriver.com, tglx@linutronix.de, julien.thierry.kdev@gmail.com MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add support to handle SGIs as regular NMIs. As SGIs or IPIs defaults to a special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI handler update in case of SGIs. Also, enable NMI support prior to gic_smp_init() as allocation of SGIs as IRQs/NMIs happen as part of this routine. Signed-off-by: Sumit Garg --- drivers/irqchip/irq-gic-v3.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 7170645..dfd8e03 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -476,6 +476,11 @@ static int gic_irq_nmi_setup(struct irq_data *d) if (WARN_ON(gic_irq(d) >= 8192)) return -EINVAL; + if (get_intid_range(d) == SGI_RANGE) { + gic_irq_set_prio(d, GICD_INT_NMI_PRI); + return 0; + } + /* desc lock should already be held */ if (gic_irq_in_rdist(d)) { u32 idx = gic_get_ppi_index(d); @@ -513,6 +518,11 @@ static void gic_irq_nmi_teardown(struct irq_data *d) if (WARN_ON(gic_irq(d) >= 8192)) return; + if (get_intid_range(d) == SGI_RANGE) { + gic_irq_set_prio(d, GICD_INT_DEF_PRI); + return; + } + /* desc lock should already be held */ if (gic_irq_in_rdist(d)) { u32 idx = gic_get_ppi_index(d); @@ -1666,6 +1676,7 @@ static int __init gic_init_bases(void __iomem *dist_base, gic_dist_init(); gic_cpu_init(); + gic_enable_nmi_support(); gic_smp_init(); gic_cpu_pm_init(); @@ -1677,8 +1688,6 @@ static int __init gic_init_bases(void __iomem *dist_base, gicv2m_init(handle, gic_data.domain); } - gic_enable_nmi_support(); - return 0; out_free: