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Sun, 13 Sep 2020 19:11:53 -0800 Received: from MTKMBS01N2.mediatek.inc (172.21.101.79) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 13 Sep 2020 20:04:49 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 14 Sep 2020 11:04:48 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 14 Sep 2020 11:04:47 +0800 From: Henry Chen To: Georgi Djakov , Rob Herring , Matthias Brugger , Viresh Kumar , Stephen Boyd , Ryan Case , Mark Brown Subject: [PATCH V5 02/17] dt-bindings: soc: Add opp table on scpsys bindings Date: Mon, 14 Sep 2020 11:04:29 +0800 Message-ID: <1600052684-21198-3-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1600052684-21198-1-git-send-email-henryc.chen@mediatek.com> References: <1600052684-21198-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 2FF2BAA8AC7D0745179B0DAD535F32421E236A189F525FC70B5002BB29ADC6572000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200913_231215_881726_F9441208 X-CRM114-Status: GOOD ( 10.69 ) X-Spam-Score: -0.2 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-0.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record 0.0 MIME_BASE64_TEXT RAW: Message text disguised using base64 encoding 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Nicolas Boichat , Mike Turquette , James Liao , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Henry Chen , Fan Chen , devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, Arvin Wang , linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add opp table on scpsys dt-bindings for Mediatek SoC. Signed-off-by: Henry Chen Reviewed-by: Rob Herring --- .../devicetree/bindings/soc/mediatek/scpsys.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt index 7f322f9..4b96fdc 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/scpsys.txt @@ -90,6 +90,27 @@ Example: <&topckgen CLK_TOP_VENC_SEL>, <&topckgen CLK_TOP_VENC_LT_SEL>; clock-names = "mfg", "mm", "venc", "venc_lt"; + operating-points-v2 = <&dvfsrc_opp_table>; + + dvfsrc_opp_table: opp-table { + compatible = "operating-points-v2-level"; + + dvfsrc_vol_min: opp1 { + opp,level = ; + }; + + dvfsrc_freq_medium: opp2 { + opp,level = ; + }; + + dvfsrc_freq_max: opp3 { + opp,level = ; + }; + + dvfsrc_vol_max: opp4 { + opp,level = ; + }; + }; }; Example(power domain sub node within power controller): @@ -151,4 +172,21 @@ Example consumer: afe: mt8173-afe-pcm@11220000 { compatible = "mediatek,mt8173-afe-pcm"; power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>; + operating-points-v2 = <&aud_opp_table>; + }; + + aud_opp_table: aud-opp-table { + compatible = "operating-points-v2"; + opp1 { + opp-hz = /bits/ 64 <793000000>; + required-opps = <&dvfsrc_vol_min>; + }; + opp2 { + opp-hz = /bits/ 64 <910000000>; + required-opps = <&dvfsrc_vol_max>; + }; + opp3 { + opp-hz = /bits/ 64 <1014000000>; + required-opps = <&dvfsrc_vol_max>; + }; };