From patchwork Fri Oct 2 04:48:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kunihiko Hayashi X-Patchwork-Id: 11812853 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E1CCD6CB for ; Fri, 2 Oct 2020 04:49:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B17B520754 for ; Fri, 2 Oct 2020 04:49:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="l/3XQvfw" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B17B520754 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FMS3AwCvkULI67aCyr7LAD76gqBG2MCYFGWwYhrLjGg=; b=l/3XQvfwD55od1W73PkD1LHWBp u+clg6aP91yLbk2SijOfQ5IB8lZWvBWZaGFSAqvjbqgNS36S1MQcElPUOmNZiIyquztZWe351yCIM 828FXxR2j+rNx9MP5Ev2jg1VoDzIAHJhcth6F8aVM/Ad+3K+AQtuHYpXefbXOpDTznO9TaFGXPN4z 3nnKSXR0+QLUZ5X7sRaI2cR8suKNj+jP6OWruYQW6nZn4KzqO9WduknCR/GXCaRW0bdkCVJWXZRTb NUcCl3j2wNJrFxxk0vDQCO0JZIZjSX1j1HYZM+W2FPK26Gf/ShLXMDw8vQZ3SFJRdqVZFuP7976Rd bIpW3MmA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kOD0K-000342-1n; Fri, 02 Oct 2020 04:49:12 +0000 Received: from mx.socionext.com ([202.248.49.38]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kOD0B-00030g-Ap for linux-arm-kernel@lists.infradead.org; Fri, 02 Oct 2020 04:49:04 +0000 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 02 Oct 2020 13:49:00 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id B9A9D180B3C; Fri, 2 Oct 2020 13:49:00 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 2 Oct 2020 13:49:00 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 1A2741A0509; Fri, 2 Oct 2020 13:49:00 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I Subject: [PATCH 3/3] PCI: uniphier-ep: Add EPC restart management support Date: Fri, 2 Oct 2020 13:48:47 +0900 Message-Id: <1601614127-13837-4-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1601614127-13837-1-git-send-email-hayashi.kunihiko@socionext.com> References: <1601614127-13837-1-git-send-email-hayashi.kunihiko@socionext.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201002_004903_534836_D5ABD3ED X-CRM114-Status: GOOD ( 24.30 ) X-Spam-Score: 0.0 (/) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (0.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.0 SPF_PASS SPF: sender matches SPF record X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kunihiko Hayashi , Masami Hiramatsu , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Set the polling function and call the init function to enable EPC restart management. The polling function detects that the bus-reset signal is a rising edge. Signed-off-by: Kunihiko Hayashi --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-uniphier-ep.c | 34 +++++++++++++++++++++++++-- 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index bc04986..4932095 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -296,6 +296,7 @@ config PCIE_UNIPHIER_EP depends on OF && HAS_IOMEM depends on PCI_ENDPOINT select PCIE_DW_EP + select PCI_ENDPOINT_RESTART help Say Y here if you want PCIe endpoint controller support on UniPhier SoCs. This driver supports Pro5 SoC. diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c index 1483559..bd187b1 100644 --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c @@ -26,6 +26,7 @@ #define PCL_RSTCTRL_PIPE3 BIT(0) #define PCL_RSTCTRL1 0x0020 +#define PCL_RSTCTRL_PERST_MON BIT(16) #define PCL_RSTCTRL_PERST BIT(0) #define PCL_RSTCTRL2 0x0024 @@ -60,6 +61,7 @@ struct uniphier_pcie_ep_priv { struct clk *clk, *clk_gio; struct reset_control *rst, *rst_gio; struct phy *phy; + bool bus_reset_status; const struct pci_epc_features *features; }; @@ -218,6 +220,23 @@ static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = { .get_features = uniphier_pcie_get_features, }; +static bool uniphier_pcie_ep_poll_reset(void *data) +{ + struct uniphier_pcie_ep_priv *priv = data; + bool ret, status; + + if (!priv) + return false; + + status = !(readl(priv->base + PCL_RSTCTRL1) & PCL_RSTCTRL_PERST_MON); + + /* return true if the rising edge of bus reset is detected */ + ret = !!(status == false && priv->bus_reset_status == true); + priv->bus_reset_status = status; + + return ret; +} + static int uniphier_add_pcie_ep(struct uniphier_pcie_ep_priv *priv, struct platform_device *pdev) { @@ -241,10 +260,21 @@ static int uniphier_add_pcie_ep(struct uniphier_pcie_ep_priv *priv, ep->addr_size = resource_size(res); ret = dw_pcie_ep_init(ep); - if (ret) + if (ret) { dev_err(dev, "Failed to initialize endpoint (%d)\n", ret); + return ret; + } - return ret; + /* Set up epc-restart thread */ + pci_epc_restart_register_poll_func(ep->epc, + uniphier_pcie_ep_poll_reset, priv); + /* With call of poll_reset() directly, initialize internal state */ + uniphier_pcie_ep_poll_reset(priv); + ret = pci_epc_restart_init(ep->epc); + if (ret) + dev_err(dev, "Failed to initialize epc-restart (%d)\n", ret); + + return 0; } static int uniphier_pcie_ep_enable(struct uniphier_pcie_ep_priv *priv)