From patchwork Thu Oct 8 10:15:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 11822599 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 17494139F for ; Thu, 8 Oct 2020 10:21:10 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 941582076B for ; Thu, 8 Oct 2020 10:21:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="lBunUG1u" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 941582076B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=YmgXrFbV+cd17zeC7W+WGU5R5oai1jsI1pFF218AEe8=; b=lBunUG1uwwDKupDlhphZJLwFl jst66n2trY4SHwQWNwvAaS+6E359bqAHS2e3iqPa3wBm6gPbuYYs5F1uC8Pln2Cwp8ZQiFyy1S2aZ u3/XaV+r3N5p1JNAksDOY5cBRUmZGi5wJTTzL/f+XuchjBkNq1+hFG/GCOsbcIjNuVgQhR1D/b2uP UJoo0K/j43ByoMGndDk89uwgC+kn/LeqiBFR5AvJ6pGJ9qZ9C6ILcj7A9GUFUn6B8bUgeunV9FnCW 3G8DX521ON2XO+p6zc+Yrbx25CkMnRrXfk3jOv8PC3ecisA3CPq65ifAbG8jMzA675XoRmH0Msagt foSQunQcQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kQT18-0008AV-2N; Thu, 08 Oct 2020 10:19:22 +0000 Received: from szxga06-in.huawei.com ([45.249.212.32] helo=huawei.com) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kQT0x-000831-7M for linux-arm-kernel@lists.infradead.org; Thu, 08 Oct 2020 10:19:12 +0000 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 4430A986425331A543F3; Thu, 8 Oct 2020 18:19:05 +0800 (CST) Received: from localhost.localdomain (10.69.192.58) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.487.0; Thu, 8 Oct 2020 18:18:59 +0800 From: John Garry To: , , , , , , , , , , Subject: [PATCH RFC v4 05/13] perf vendor events arm64: Add Architected events smmuv3-pmcg.json Date: Thu, 8 Oct 2020 18:15:13 +0800 Message-ID: <1602152121-240367-6-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1602152121-240367-1-git-send-email-john.garry@huawei.com> References: <1602152121-240367-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.58] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201008_061911_562561_03E107A5 X-CRM114-Status: GOOD ( 13.20 ) X-Spam-Score: -2.3 (--) X-Spam-Report: SpamAssassin version 3.4.4 on merlin.infradead.org summary: Content analysis details: (-2.3 points) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [45.249.212.32 listed in list.dnswl.org] 0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [45.249.212.32 listed in wl.mailspike.net] -0.0 SPF_PASS SPF: sender matches SPF record -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, John Garry , qiangqing.zhang@nxp.com, linuxarm@huawei.com, zhangshaokun@hisilicon.com, james.clark@arm.com, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patchwork-linux-arm=patchwork.kernel.org@lists.infradead.org Add JSON for Architected events from [0], Section 10.3 . [0] https://static.docs.arm.com/ihi0070/a/IHI_0070A_SMMUv3.pdf Signed-off-by: John Garry --- .../pmu-events/arch/arm64/smmuv3-pmcg.json | 58 +++++++++++++++++++ tools/perf/pmu-events/jevents.c | 2 + 2 files changed, 60 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json diff --git a/tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json b/tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json new file mode 100644 index 000000000000..8a59ce48bf06 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/smmuv3-pmcg.json @@ -0,0 +1,58 @@ +[ + { + "PublicDescription": "Clock cycles", + "EventCode": "0x00", + "EventName": "smmuv3_pmcg.CYCLES", + "BriefDescription": "Clock cycles" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "Transaction", + "EventCode": "0x01", + "EventName": "smmuv3_pmcg.TRANSACTION", + "BriefDescription": "Transaction" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "TLB miss caused by incoming transaction or (ATS or non-ATS) translation request", + "EventCode": "0x02", + "EventName": "smmuv3_pmcg.TLB_MISS", + "BriefDescription": "TLB miss caused by incoming transaction or (ATS or non-ATS) translation request" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "Configuration cache miss caused by transaction or(ATS or non-ATS)translation request", + "EventCode": "0x03", + "EventName": "smmuv3_pmcg.CONFIG_CACHE_MISS", + "BriefDescription": "Configuration cache miss caused by transaction or(ATS or non-ATS)translation request" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "Translation table walk access", + "EventCode": "0x04", + "EventName": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS", + "BriefDescription": "Translation table walk access" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "Configuration structure access", + "EventCode": "0x05", + "EventName": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS", + "BriefDescription": "Configuration structure access" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "PCIe ATS Translation Request received", + "EventCode": "0x06", + "EventName": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ", + "BriefDescription": "PCIe ATS Translation Request received" + "Unit": "smmuv3_pmcg", + }, + { + "PublicDescription": "PCIe ATS Translated Transaction passed through SMMU", + "EventCode": "0x07", + "EventName": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED", + "BriefDescription": "PCIe ATS Translated Transaction passed through SMMU" + "Unit": "smmuv3_pmcg", + } +] diff --git a/tools/perf/pmu-events/jevents.c b/tools/perf/pmu-events/jevents.c index a1a4bc543a80..2e581bd9b0a6 100644 --- a/tools/perf/pmu-events/jevents.c +++ b/tools/perf/pmu-events/jevents.c @@ -256,6 +256,8 @@ static struct map { { "hisi_sccl,ddrc", "hisi_sccl,ddrc" }, { "hisi_sccl,hha", "hisi_sccl,hha" }, { "hisi_sccl,l3c", "hisi_sccl,l3c" }, + /* it's not realistic to keep adding these, we need something more scalable ... */ + { "smmuv3_pmcg", "smmuv3_pmcg" }, { "L3PMC", "amd_l3" }, {} };