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Thu, 22 Oct 2020 20:56:08 +0800 From: Weiyi Lu To: Matthias Brugger , Stephen Boyd , Nicolas Boichat Subject: [PATCH 12/12] clk: mediatek: limit en_mask to a pure div_en_mask Date: Thu, 22 Oct 2020 20:56:05 +0800 Message-ID: <1603371365-30863-13-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1603371365-30863-1-git-send-email-weiyi.lu@mediatek.com> References: <1603371365-30863-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201022_090617_018332_BA6C3AAB X-CRM114-Status: GOOD ( 13.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Because all pll data has been updated. We no longer allow en_mask is a combination of pll_en_bit and div_en_mask. Signed-off-by: Weiyi Lu --- drivers/clk/mediatek/clk-pll.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 11ed5d1..e0b00bc 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -238,7 +238,6 @@ static int mtk_pll_prepare(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); u32 r; - u32 div_en_mask; r = readl(pll->pwr_addr) | CON0_PWR_ON; writel(r, pll->pwr_addr); @@ -251,9 +250,8 @@ static int mtk_pll_prepare(struct clk_hw *hw) r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN; writel(r, pll->base_addr + REG_CON0); - div_en_mask = pll->data->en_mask & ~CON0_BASE_EN; - if (div_en_mask) { - r = readl(pll->base_addr + REG_CON0) | div_en_mask; + if (pll->data->en_mask) { + r = readl(pll->base_addr + REG_CON0) | pll->data->en_mask; writel(r, pll->base_addr + REG_CON0); } @@ -274,7 +272,6 @@ static void mtk_pll_unprepare(struct clk_hw *hw) { struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); u32 r; - u32 div_en_mask; if (pll->data->flags & HAVE_RST_BAR) { r = readl(pll->base_addr + REG_CON0); @@ -284,9 +281,8 @@ static void mtk_pll_unprepare(struct clk_hw *hw) __mtk_pll_tuner_disable(pll); - div_en_mask = pll->data->en_mask & ~CON0_BASE_EN; - if (div_en_mask) { - r = readl(pll->base_addr + REG_CON0) & ~div_en_mask; + if (pll->data->en_mask) { + r = readl(pll->base_addr + REG_CON0) & ~pll->data->en_mask; writel(r, pll->base_addr + REG_CON0); }