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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: QzyrjNZ75D/T6Zuz/QP/5hxb4SFCu0QGU6jdGWrjmbuxNkC7MhOVJ50uOwbzGi6VgKW0FJeCUdessaeY6Hypa3uv6rAWfW2xcVuse4twTbTerniMpGXShYBzylxL5nINpT4ijlzyYqmSnACYhRzgJeZioqiRtNX+nUeeExzvfUsp4IlSqd+9yJ4PjJU02qrMvTV+dRbTBqSc/u49BgJ+oeETsmrY6iz/ghTlJXpWWj6/7WUsLNA/58eyaxLfnlaoe/drvAHrzrO/RCop4w6pPaL735pIm9HjzPtH5arB5P2r82iEUq1dQ0SC/4mNDgUn3Uq1ZxhGtVRj2vBisVd3zs4qxpIQ9kBJgq5JUgn6H/t3iKYyCG1ldkVoEmn0DlXcpunpJZgJ8wuYPg7XhgCyXMU4YbQF1TE3t5PEh7AUQenCmnUisLgobqZmBo5em7zNpmIwFTjorE7+he7Dm7AiMEkH9umoTzYr3T0OeVftQmZTfqgoWJWJohrgGFnai6raBpqNRAZNREIHkTeJnIMBADh5xYZHgRxgksXYzamDtvpDHipSdo9fPbSj5Q0qcACPssRF08ZlqBqv+H8C71qsNcbrUTmCcYgUj1h4let6qEmuixqAEnHUxx7+ln2IMPdqQOPHqwDIXP8qngQo00/L5w== X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0ce8f45e-fa71-4793-6d67-08d88b9d5a23 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2020 08:38:41.4740 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 0UXg0vxkUmi7DY4j6CAlxsNAdkSKBbX0n+HLei7xM84umtHpXAxgui1p9orxwvsAni2ypfogYN2aUo+u2icX0g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6990 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201118_033844_038587_C437BE39 X-CRM114-Status: GOOD ( 17.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aisheng.dong@nxp.com, sboyd@kernel.org, shawnguo@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org, linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com, s.hauer@pengutronix.de Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds LPCG clocks support for display controller of i.MX8qxp SoC. Cc: Michael Turquette Cc: Stephen Boyd Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: Rob Herring Cc: Dong Aisheng Signed-off-by: Liu Ying --- drivers/clk/imx/clk-imx8qxp-lpcg.c | 41 ++++++++++++++++++++++++++++++++++ drivers/clk/imx/clk-imx8qxp-lpcg.h | 20 +++++++++++++++++ include/dt-bindings/clock/imx8-clock.h | 35 +++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c index d3e905c..176d426 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c @@ -115,6 +115,46 @@ static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = { .num_max = IMX_CONN_LPCG_CLK_END, }; +static const struct imx8qxp_lpcg_data imx8qxp_lpcg_dc[] = { + { IMX_DC0_LPCG_DISP0_CLK, "dc0_lpcg_disp0_clk", "dc0_disp0_clk", 0, DC_DISP_LPCG, 0, 0, }, + { IMX_DC0_LPCG_DISP1_CLK, "dc0_lpcg_disp1_clk", "dc0_disp1_clk", 0, DC_DISP_LPCG, 4, 0, }, + { IMX_DC0_LPCG_LIS_IPG_CLK, "dc0_lpcg_lis_ipg_clk", "dc_cfg_clk_root", 0, DC_LIS_IPG_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DISP_CTL_LINK_MST0_CLK, "dc0_lpcg_disp_ctl_link_mst0_clk", "dc_cfg_clk_root", 0, DC_DISP_CTL_LINK_MST0_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PIX_COMBINER_APB_CLK, "dc0_lpcg_pix_combiner_apb_clk", "dc_cfg_clk_root", 0, DC_PIX_COMBINER_APB_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DC_AXI_CLK, "dc0_lpcg_dc_axi_clk", "dc_axi_int_clk_root", 0, DC_AXI_CFG_LPCG, 20, 0, }, + { IMX_DC0_LPCG_DC_CFG_CLK, "dc0_lpcg_dc_cfg_clk", "dc_cfg_clk_root", 0, DC_AXI_CFG_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DPR0_APB_CLK, "dc0_lpcg_dpr0_apb_clk", "dc_cfg_clk_root", 0, DC_DPR0_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DPR0_B_CLK, "dc0_lpcg_dpr0_b_clk", "dc_axi_ext_clk_root", 0, DC_DPR0_LPCG, 20, 0, }, + { IMX_DC0_LPCG_RTRAM0_CLK, "dc0_lpcg_rtram0_clk", "dc_axi_int_clk_root", 0, DC_RTRAM0_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG0_RTRAM_CLK, "dc0_lpcg_prg0_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG0_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG0_APB_CLK, "dc0_lpcg_prg0_apb_clk", "dc_cfg_clk_root", 0, DC_PRG0_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG1_RTRAM_CLK, "dc0_lpcg_prg1_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG1_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG1_APB_CLK, "dc0_lpcg_prg1_apb_clk", "dc_cfg_clk_root", 0, DC_PRG1_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG2_RTRAM_CLK, "dc0_lpcg_prg2_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG2_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG2_APB_CLK, "dc0_lpcg_prg2_apb_clk", "dc_cfg_clk_root", 0, DC_PRG2_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DPR1_APB_CLK, "dc0_lpcg_dpr1_apb_clk", "dc_cfg_clk_root", 0, DC_DPR1_LPCG, 16, 0, }, + { IMX_DC0_LPCG_DPR1_B_CLK, "dc0_lpcg_dpr1_b_clk", "dc_axi_ext_clk_root", 0, DC_DPR1_LPCG, 20, 0, }, + { IMX_DC0_LPCG_RTRAM1_CLK, "dc0_lpcg_rtram1_clk", "dc_axi_int_clk_root", 0, DC_RTRAM1_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG3_RTRAM_CLK, "dc0_lpcg_prg3_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG3_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG3_APB_CLK, "dc0_lpcg_prg3_apb_clk", "dc_cfg_clk_root", 0, DC_PRG3_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG4_RTRAM_CLK, "dc0_lpcg_prg4_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG4_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG4_APB_CLK, "dc0_lpcg_prg4_apb_clk", "dc_cfg_clk_root", 0, DC_PRG4_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG5_RTRAM_CLK, "dc0_lpcg_prg5_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG5_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG5_APB_CLK, "dc0_lpcg_prg5_apb_clk", "dc_cfg_clk_root", 0, DC_PRG5_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG6_RTRAM_CLK, "dc0_lpcg_prg6_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG6_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG6_APB_CLK, "dc0_lpcg_prg6_apb_clk", "dc_cfg_clk_root", 0, DC_PRG6_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG7_RTRAM_CLK, "dc0_lpcg_prg7_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG7_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG7_APB_CLK, "dc0_lpcg_prg7_apb_clk", "dc_cfg_clk_root", 0, DC_PRG7_LPCG, 16, 0, }, + { IMX_DC0_LPCG_PRG8_RTRAM_CLK, "dc0_lpcg_prg8_rtram_clk", "dc_axi_int_clk_root", 0, DC_PRG8_LPCG, 0, 0, }, + { IMX_DC0_LPCG_PRG8_APB_CLK, "dc0_lpcg_prg8_apb_clk", "dc_cfg_clk_root", 0, DC_PRG8_LPCG, 16, 0, }, +}; + +static const struct imx8qxp_ss_lpcg imx8qxp_ss_dc = { + .lpcg = imx8qxp_lpcg_dc, + .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_dc), + .num_max = IMX_DC0_LPCG_CLK_END, +}; + static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = { { IMX_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, }, { IMX_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, }, @@ -355,6 +395,7 @@ static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev) static const struct of_device_id imx8qxp_lpcg_match[] = { { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, }, { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, }, + { .compatible = "fsl,imx8qxp-lpcg-dc", &imx8qxp_ss_dc, }, { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, }, { .compatible = "fsl,imx8qxp-lpcg", NULL }, { /* sentinel */ } diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.h b/drivers/clk/imx/clk-imx8qxp-lpcg.h index 2a37ce5..e1423a9 100644 --- a/drivers/clk/imx/clk-imx8qxp-lpcg.h +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.h @@ -99,4 +99,24 @@ #define ADMA_FLEXCAN_1_LPCG 0x1ce0000 #define ADMA_FLEXCAN_2_LPCG 0x1cf0000 +/* Display SS */ +#define DC_DISP_LPCG 0x00 +#define DC_LIS_IPG_LPCG 0x04 +#define DC_DISP_CTL_LINK_MST0_LPCG 0x08 +#define DC_PIX_COMBINER_APB_LPCG 0x10 +#define DC_AXI_CFG_LPCG 0x14 +#define DC_DPR0_LPCG 0x18 +#define DC_RTRAM0_LPCG 0x1c +#define DC_PRG0_LPCG 0x20 +#define DC_PRG1_LPCG 0x24 +#define DC_PRG2_LPCG 0x28 +#define DC_DPR1_LPCG 0x2c +#define DC_RTRAM1_LPCG 0x30 +#define DC_PRG3_LPCG 0x34 +#define DC_PRG4_LPCG 0x38 +#define DC_PRG5_LPCG 0x3c +#define DC_PRG6_LPCG 0x40 +#define DC_PRG7_LPCG 0x44 +#define DC_PRG8_LPCG 0x48 + #endif /* _IMX8QXP_LPCG_H */ diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h index 673a8c6..c9dd0c6 100644 --- a/include/dt-bindings/clock/imx8-clock.h +++ b/include/dt-bindings/clock/imx8-clock.h @@ -290,4 +290,39 @@ #define IMX_ADMA_LPCG_CLK_END 45 +/* DC0 SS LPCG */ +#define IMX_DC0_LPCG_DISP0_CLK 0 +#define IMX_DC0_LPCG_DISP1_CLK 1 +#define IMX_DC0_LPCG_LIS_IPG_CLK 2 +#define IMX_DC0_LPCG_DISP_CTL_LINK_MST0_CLK 3 +#define IMX_DC0_LPCG_PIX_COMBINER_APB_CLK 4 +#define IMX_DC0_LPCG_DC_AXI_CLK 5 +#define IMX_DC0_LPCG_DC_CFG_CLK 6 +#define IMX_DC0_LPCG_DPR0_APB_CLK 7 +#define IMX_DC0_LPCG_DPR0_B_CLK 8 +#define IMX_DC0_LPCG_RTRAM0_CLK 9 +#define IMX_DC0_LPCG_PRG0_RTRAM_CLK 10 +#define IMX_DC0_LPCG_PRG0_APB_CLK 11 +#define IMX_DC0_LPCG_PRG1_RTRAM_CLK 12 +#define IMX_DC0_LPCG_PRG1_APB_CLK 13 +#define IMX_DC0_LPCG_PRG2_RTRAM_CLK 14 +#define IMX_DC0_LPCG_PRG2_APB_CLK 15 +#define IMX_DC0_LPCG_DPR1_APB_CLK 16 +#define IMX_DC0_LPCG_DPR1_B_CLK 17 +#define IMX_DC0_LPCG_RTRAM1_CLK 18 +#define IMX_DC0_LPCG_PRG3_RTRAM_CLK 19 +#define IMX_DC0_LPCG_PRG3_APB_CLK 20 +#define IMX_DC0_LPCG_PRG4_RTRAM_CLK 21 +#define IMX_DC0_LPCG_PRG4_APB_CLK 22 +#define IMX_DC0_LPCG_PRG5_RTRAM_CLK 23 +#define IMX_DC0_LPCG_PRG5_APB_CLK 24 +#define IMX_DC0_LPCG_PRG6_RTRAM_CLK 25 +#define IMX_DC0_LPCG_PRG6_APB_CLK 26 +#define IMX_DC0_LPCG_PRG7_RTRAM_CLK 27 +#define IMX_DC0_LPCG_PRG7_APB_CLK 28 +#define IMX_DC0_LPCG_PRG8_RTRAM_CLK 29 +#define IMX_DC0_LPCG_PRG8_APB_CLK 30 + +#define IMX_DC0_LPCG_CLK_END 31 + #endif /* __DT_BINDINGS_CLOCK_IMX_H */