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dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) by VI1PR0402MB2879.eurprd04.prod.outlook.com (2603:10a6:800:b7::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.23; Thu, 3 Dec 2020 03:14:32 +0000 Received: from VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685]) by VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685%7]) with mapi id 15.20.3611.025; Thu, 3 Dec 2020 03:14:32 +0000 From: Liu Ying To: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] dt-bindings: display: imx: Add i.MX8qxp/qm DPR channel binding Date: Thu, 3 Dec 2020 11:06:28 +0800 Message-Id: <1606964791-24927-4-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606964791-24927-1-git-send-email-victor.liu@nxp.com> References: <1606964791-24927-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR02CA0028.apcprd02.prod.outlook.com (2603:1096:3:18::16) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR02CA0028.apcprd02.prod.outlook.com (2603:1096:3:18::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3632.17 via Frontend Transport; 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Signed-off-by: Liu Ying --- Note that this depends on the 'two cell binding' clock patch set which has already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h won't be found. v1->v2: * Use new dt binding way to add clocks in the example. .../bindings/display/imx/fsl,imx8qxp-dprc.yaml | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml new file mode 100644 index 00000000..91e9472 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dprc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-dprc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Channel + +maintainers: + - Liu Ying + +description: | + The i.MX8qm/qxp Display Prefetch Resolve Channel(DPRC) is an engine which + fetches display data before the display pipeline needs the data to drive + pixels in the active display region. This data is transformed, or resolved, + from a variety of tiled buffer formats into linear format, if needed. + The DPR works with a double bank memory structure. This memory structure is + implemented in the Resolve Tile Memory(RTRAM) and the banks are referred to + as A and B. Each bank is either 4 or 8 lines high depending on the source + frame buffer format. + +properties: + compatible: + oneOf: + - const: fsl,imx8qxp-dpr-channel + - const: fsl,imx8qm-dpr-channel + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: apb clock + - description: b clock + - description: rtram clock + + clock-names: + items: + - const: apb + - const: b + - const: rtram + + fsl,sc-resource: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The SCU resource ID associated with this DPRC instance. + + fsl,prgs: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: | + List of phandle which points to Prefetch Resolve Gaskets(PRGs) + associated with this DPRC instance. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - fsl,sc-resource + - fsl,prgs + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + #include + dpr-channel@56100000 { + compatible = "fsl,imx8qxp-dpr-channel"; + reg = <0x56100000 0x10000>; + interrupts = ; + clocks = <&dc0_dpr1_lpcg IMX_LPCG_CLK_4>, + <&dc0_dpr1_lpcg IMX_LPCG_CLK_5>, + <&dc0_rtram1_lpcg IMX_LPCG_CLK_0>; + clock-names = "apb", "b", "rtram"; + fsl,sc-resource = ; + fsl,prgs = <&dc0_prg4>, <&dc0_prg5>; + power-domains = <&pd IMX_SC_R_DC_0>; + };