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dmarc=none action=none header.from=nxp.com; Received: from VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) by VI1PR0402MB2816.eurprd04.prod.outlook.com (2603:10a6:800:b7::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3654.17; Fri, 18 Dec 2020 03:32:54 +0000 Received: from VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685]) by VI1PR04MB3983.eurprd04.prod.outlook.com ([fe80::dcb7:6117:3def:2685%7]) with mapi id 15.20.3654.024; Fri, 18 Dec 2020 03:32:54 +0000 From: Liu Ying To: linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 2/6] dt-bindings: display: imx: Add i.MX8qxp/qm PRG binding Date: Fri, 18 Dec 2020 11:23:49 +0800 Message-Id: <1608261833-24772-3-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1608261833-24772-1-git-send-email-victor.liu@nxp.com> References: <1608261833-24772-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR02CA0118.apcprd02.prod.outlook.com (2603:1096:4:92::34) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2PR02CA0118.apcprd02.prod.outlook.com (2603:1096:4:92::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3676.28 via Frontend Transport; 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Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- Note that this depends on the 'two cell binding' clock patch set which has already landed in Shawn's i.MX clk/imx git branch. Otherwise, imx8-lpcg.h won't be found. v4->v5: * No change. v3->v4: * Improve compatible property by using enum instead of oneOf+const. (Rob) * Add Rob's R-b tag. v2->v3: * No change. v1->v2: * Use new dt binding way to add clocks in the example. .../bindings/display/imx/fsl,imx8qxp-prg.yaml | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml new file mode 100644 index 00000000..3ff46e0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-prg.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx8qxp-prg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Prefetch Resolve Gasket + +maintainers: + - Liu Ying + +description: | + The i.MX8qm/qxp Prefetch Resolve Gasket (PRG) is a gasket interface between + RTRAM controller and Display Controller. The main function is to convert + the AXI interface to the RTRAM interface, which includes re-mapping the + ARADDR to a RTRAM address. + +properties: + compatible: + enum: + - fsl,imx8qxp-prg + - fsl,imx8qm-prg + + reg: + maxItems: 1 + + clocks: + items: + - description: rtram clock + - description: apb clock + + clock-names: + items: + - const: rtram + - const: apb + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + #include + #include + prg@56040000 { + compatible = "fsl,imx8qxp-prg"; + reg = <0x56040000 0x10000>; + clocks = <&dc0_prg0_lpcg IMX_LPCG_CLK_0>, + <&dc0_prg0_lpcg IMX_LPCG_CLK_4>; + clock-names = "rtram", "apb"; + power-domains = <&pd IMX_SC_R_DC_0>; + };