From patchwork Tue Dec 22 13:40:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiyi Lu X-Patchwork-Id: 11986669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2E6DC433E0 for ; Tue, 22 Dec 2020 13:41:55 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9E0EF23103 for ; Tue, 22 Dec 2020 13:41:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9E0EF23103 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3W3nwBJ9+a2bZpcydDLJemuwMH0hEz6dlioDjWxGxgk=; b=wv8CSiDf6FwqsACHxYMApDjd0 MM8zlj+KyUQ7YQqFbYTGz5kn2GqbG0w3CjE2n8kw4Rsjcb8qzDuUWIPXsV20aCvBXXrBfVlF0fpv4 icCx09K3tkkRSTzx5S9z6Lwir34cGhnVErVUPPD8/TY84jCYr98M8W0DNUcKT9xrmYda8y7Pj4Vr1 4fypq/AuKms60TEC3z1GAd8XO2uTVwP8JKns/FwHs+bVnJbxsPuojpDWYACHisT2ul/yUQs6la1tt 6gY+1Vo2Qrum9rs41mvnHpdYKpr+Mfvm/VHFOh7fz7XaNpO0geGxacanbKs28mje0lxFHiXpif7z/ xKVvvnwoA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1krhu5-0001XH-JR; Tue, 22 Dec 2020 13:40:41 +0000 Received: from mailgw02.mediatek.com ([216.200.240.185]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1krhtu-0001RZ-0O; Tue, 22 Dec 2020 13:40:31 +0000 X-UUID: c103924649f34f95b1f83bd7b8582025-20201222 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=P9qCPMdBsYu+jfoLURZnh7M+pHNHP530VcNCvuHG/U0=; b=G4yNQAKo6Z+gwLucg53jNk4hFYTXoGnvkEu5p3Rhp0C8Ie1k8H34ZHEaYY2A8sdIot2sLX/48ZgHSRky8HDsgCrstjgQ1FsgvpF5kkL7jSI+FEpOOTjS/0+YZuIgkpo70GrJdOyBuB2IgnuXm7ywEUKaJveEK1QOv8JVbR+QRKs=; X-UUID: c103924649f34f95b1f83bd7b8582025-20201222 Received: from mtkcas66.mediatek.inc [(172.29.193.44)] by mailgw02.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 896599353; Tue, 22 Dec 2020 05:40:19 -0800 Received: from MTKMBS07N2.mediatek.inc (172.21.101.141) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Dec 2020 05:40:16 -0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Dec 2020 21:40:13 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 22 Dec 2020 21:40:12 +0800 From: Weiyi Lu To: Matthias Brugger , Rob Herring , Nicolas Boichat Subject: [PATCH 1/2] arm64: dts: mediatek: Add mt8192 clock controllers Date: Tue, 22 Dec 2020 21:40:13 +0800 Message-ID: <1608644414-17793-2-git-send-email-weiyi.lu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1608644414-17793-1-git-send-email-weiyi.lu@mediatek.com> References: <1608644414-17793-1-git-send-email-weiyi.lu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201222_084030_261192_28E80197 X-CRM114-Status: GOOD ( 11.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Weiyi Lu , srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add clock controller nodes for SoC mt8192 Signed-off-by: Weiyi Lu --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163 +++++++++++++++++++++++++++++++ 1 file changed, 163 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index e12e024..92dcfbd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -5,6 +5,7 @@ */ /dts-v1/; +#include #include #include #include @@ -213,6 +214,24 @@ }; }; + topckgen: syscon@10000000 { + compatible = "mediatek,mt8192-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8192-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8192-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + pio: pinctrl@10005000 { compatible = "mediatek,mt8192-pinctrl"; reg = <0 0x10005000 0 0x1000>, @@ -238,6 +257,12 @@ #interrupt-cells = <2>; }; + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8192-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + systimer: timer@10017000 { compatible = "mediatek,mt8192-timer", "mediatek,mt6765-timer"; @@ -247,6 +272,12 @@ clock-names = "clk13m"; }; + scp_adsp: syscon@10720000 { + compatible = "mediatek,mt8192-scp_adsp", "syscon"; + reg = <0 0x10720000 0 0x1000>; + #clock-cells = <1>; + }; + uart0: serial@11002000 { compatible = "mediatek,mt8192-uart", "mediatek,mt6577-uart"; @@ -267,6 +298,12 @@ status = "disabled"; }; + imp_iic_wrap_c: syscon@11007000 { + compatible = "mediatek,mt8192-imp_iic_wrap_c", "syscon"; + reg = <0 0x11007000 0 0x1000>; + #clock-cells = <1>; + }; + spi0: spi@1100a000 { compatible = "mediatek,mt8192-spi", "mediatek,mt6765-spi"; @@ -379,6 +416,12 @@ status = "disabled"; }; + audsys: syscon@11210000 { + compatible = "mediatek,mt8192-audsys", "syscon"; + reg = <0 0x11210000 0 0x1000>; + #clock-cells = <1>; + }; + i2c3: i2c3@11cb0000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11cb0000 0 0x1000>, @@ -392,6 +435,12 @@ status = "disabled"; }; + imp_iic_wrap_e: syscon@11cb1000 { + compatible = "mediatek,mt8192-imp_iic_wrap_e", "syscon"; + reg = <0 0x11cb1000 0 0x1000>; + #clock-cells = <1>; + }; + i2c7: i2c7@11d00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d00000 0 0x1000>, @@ -431,6 +480,12 @@ status = "disabled"; }; + imp_iic_wrap_s: syscon@11d03000 { + compatible = "mediatek,mt8192-imp_iic_wrap_s", "syscon"; + reg = <0 0x11d03000 0 0x1000>; + #clock-cells = <1>; + }; + i2c1: i2c1@11d20000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11d20000 0 0x1000>, @@ -470,6 +525,12 @@ status = "disabled"; }; + imp_iic_wrap_ws: syscon@11d23000 { + compatible = "mediatek,mt8192-imp_iic_wrap_ws", "syscon"; + reg = <0 0x11d23000 0 0x1000>; + #clock-cells = <1>; + }; + i2c5: i2c5@11e00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11e00000 0 0x1000>, @@ -483,6 +544,12 @@ status = "disabled"; }; + imp_iic_wrap_w: syscon@11e01000 { + compatible = "mediatek,mt8192-imp_iic_wrap_w", "syscon"; + reg = <0 0x11e01000 0 0x1000>; + #clock-cells = <1>; + }; + i2c0: i2c0@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, @@ -508,5 +575,101 @@ #size-cells = <0>; status = "disabled"; }; + + imp_iic_wrap_n: syscon@11f02000 { + compatible = "mediatek,mt8192-imp_iic_wrap_n", "syscon"; + reg = <0 0x11f02000 0 0x1000>; + #clock-cells = <1>; + }; + + msdc_top: syscon@11f10000 { + compatible = "mediatek,mt8192-msdc_top", "syscon"; + reg = <0 0x11f10000 0 0x1000>; + #clock-cells = <1>; + }; + + msdc: syscon@11f60000 { + compatible = "mediatek,mt8192-msdc", "syscon"; + reg = <0 0x11f60000 0 0x1000>; + #clock-cells = <1>; + }; + + mfgcfg: syscon@13fbf000 { + compatible = "mediatek,mt8192-mfgcfg", "syscon"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8192-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: syscon@15020000 { + compatible = "mediatek,mt8192-imgsys", "syscon"; + reg = <0 0x15020000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys2: syscon@15820000 { + compatible = "mediatek,mt8192-imgsys2", "syscon"; + reg = <0 0x15820000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys_soc: syscon@1600f000 { + compatible = "mediatek,mt8192-vdecsys_soc", "syscon"; + reg = <0 0x1600f000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@1602f000 { + compatible = "mediatek,mt8192-vdecsys", "syscon"; + reg = <0 0x1602f000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt8192-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: syscon@1a000000 { + compatible = "mediatek,mt8192-camsys", "syscon"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawa: syscon@1a04f000 { + compatible = "mediatek,mt8192-camsys_rawa", "syscon"; + reg = <0 0x1a04f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: syscon@1a06f000 { + compatible = "mediatek,mt8192-camsys_rawb", "syscon"; + reg = <0 0x1a06f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawc: syscon@1a08f000 { + compatible = "mediatek,mt8192-camsys_rawc", "syscon"; + reg = <0 0x1a08f000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: syscon@1b000000 { + compatible = "mediatek,mt8192-ipesys", "syscon"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + + mdpsys: syscon@1f000000 { + compatible = "mediatek,mt8192-mdpsys", "syscon"; + reg = <0 0x1f000000 0 0x1000>; + #clock-cells = <1>; + }; }; };