From patchwork Wed Feb 3 07:51:08 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 12063655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A991C433DB for ; Wed, 3 Feb 2021 07:53:45 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F3FCD64DE7 for ; Wed, 3 Feb 2021 07:53:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F3FCD64DE7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-ID:Date: Subject:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=XxjO8dtONaLjojlyKwode1WvjB22HA6j6GORYWYecFQ=; b=ESNY1Fqjq2MtOhtJB+LHdu5pK apS10zDSU/93MJbLIsQw6v+7itWncQg8iT3I2jpoh6cvAVdVT+rIrkLOdX6o8bMfOYp97MQkdvC+Z 5AOs1Ey5y7s77f7GzzIxuywnwONRxYqJfcBNLoC9Sn/7JuHemQbPvMrkmLZKz/4TNWC+24JdyDRXq +ypbpOd4aBaEDI28CbmnApYhwL9taF6KoiJ5/djAFKvr5VLS6kElj2F1uRl/Uf01Eh8lh/qU0aZlG tqGljkA2L20eZROBcXO/OZu2cNknMDyb0l5b/CdNwbRffRNYEEtXGbjIrifouY78nPxXKNrZfpgjR 6qmTVmeNQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7Cxj-0000Md-Ci; Wed, 03 Feb 2021 07:52:31 +0000 Received: from szxga07-in.huawei.com ([45.249.212.35]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7CxS-0000Ba-Gw for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2021 07:52:16 +0000 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga07-in.huawei.com (SkyGuard) with ESMTP id 4DVv4Y3MRYz7gQv; Wed, 3 Feb 2021 15:50:53 +0800 (CST) Received: from localhost.localdomain (10.69.192.56) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.498.0; Wed, 3 Feb 2021 15:52:00 +0800 From: Shaokun Zhang To: Subject: [PATCH v2 8/8] docs: perf: Add new description on HiSilicon uncore PMU v2 Date: Wed, 3 Feb 2021 15:51:08 +0800 Message-ID: <1612338668-40493-9-git-send-email-zhangshaokun@hisilicon.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612338668-40493-1-git-send-email-zhangshaokun@hisilicon.com> References: <1612338668-40493-1-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 X-Originating-IP: [10.69.192.56] X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210203_025215_642241_A60D5E78 X-CRM114-Status: GOOD ( 15.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Qi Liu , John Garry , Shaokun Zhang , Jonathan Cameron , Will Deacon Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Some news functions are added on HiSilicon uncore PMUs. Document them to provide guidance on how to use them. Cc: Mark Rutland Cc: Will Deacon Cc: John Garry Cc: Jonathan Cameron Reviewed-by: John Garry Co-developed-by: Qi Liu Signed-off-by: Qi Liu Signed-off-by: Shaokun Zhang --- Documentation/admin-guide/perf/hisi-pmu.rst | 54 +++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst index 404a5c3d9d00..47aadbcda301 100644 --- a/Documentation/admin-guide/perf/hisi-pmu.rst +++ b/Documentation/admin-guide/perf/hisi-pmu.rst @@ -53,6 +53,60 @@ Example usage of perf:: $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5 +For HiSilicon uncore PMU v2 whose identifier is 0x30, the topology is the same +as PMU v1, but some new functions are added to the hardware. + +(a) L3C PMU supports filtering by core/thread within the cluster which can be +specified as a bitmap. + $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5 +This will only count the operations from core/thread 0 and 1 in this cluster. + +(b) Tracetag allow the user to chose to count only read, write or atomic +operations via the tt_req parameeter in perf. The default value counts all +operations. tt_req is 3bits, 3'b100 represents read operations, 3'b101 +represents write operations, 3'b110 represents atomic store operations and +3'b111 represents atomic non-store operations, other values are reserved. + $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5 +This will only count the read operations in this cluster. + +(c) Datasrc allows the user to check where the data comes from. It is 5 bits. +Some important codes are as follows: +5'b00001: comes from L3C in this die; +5'b01000: comes from L3C in the cross-die; +5'b01001: comes from L3C which is in another socket; +5'b01110: comes from the local DDR; +5'b01111: comes from the cross-die DDR; +5'b10000: comes from cross-socket DDR; +etc, it is mainly helpful to find that the data source is nearest from the CPU +cores. If datasrc is used in the multi-chips, the ds_skt shall be configured in +perf command. + $# perf stat -a -e hisi_sccl3_l3c0/config=0xb9,ds_cfg=0xE/, + hisi_sccl3_l3c0/config=0xb9,ds_cfg=0xF/ sleep 5 + +(d)Some HiSilicon SoCs encapsulate multiple CPU and IO dies. Each CPU die contains +many Compute Clusters (CCLs). The I/O dies are called Super I/O clusters (SICL) +containing multiple I/O clusters (ICLs). Each CCL/ICL in the SoC has a +unique master-ID. The uncore PMU can filter by specified master-ID or +combination of master-IDs. The master-ID is 14bits of which the lower 3-bits +specify the individual core within a CCL. The upper 11 bits include a +6-bit SCCL-ID and 5-bit CCL/ICL-ID. +The user may filter by a specific CCL/ICL through the mstid_cmd and mstid_msk +parameters. A set bit in mstid_mask means the PMU will not check the bit when +matching against the mstid_cmd. + +(e) For new uncore PMU, SLLC and PA, normal PMU events are supported and other +new functions are also added simultaneously, such as, tgt_id and src_id can +be determined by the requirements which are also 11-bits including SCCL-ID and +CCL/ICL-ID. For I/O die, the ICL-ID is followed by: +5'b00000: I/O_MGMT_ICL; +5'b00001: Network_ICL; +5'b00011: HAC_ICL; +5'b10000: PCIe_ICL; + +If all of these options are disabled, it can works by the default value that +doesn't distinguish the filter condition and ID information and will return +the total counter values in the PMU counters. + The current driver does not support sampling. So "perf record" is unsupported. Also attach to a task is unsupported as the events are all uncore.