From patchwork Fri Mar 5 13:17:37 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aisheng Dong X-Patchwork-Id: 12118487 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70F70C433E6 for ; Fri, 5 Mar 2021 13:34:48 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9646B64FE4 for ; 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Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lIAZO-00F6Hj-10; Fri, 05 Mar 2021 13:32:42 +0000 Received: from inva020.nxp.com ([92.121.34.13]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lIAXd-00F5ux-M3 for linux-arm-kernel@lists.infradead.org; Fri, 05 Mar 2021 13:30:55 +0000 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2F2A11A144B; Fri, 5 Mar 2021 14:30:53 +0100 (CET) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3FDD81A0EAC; Fri, 5 Mar 2021 14:30:47 +0100 (CET) Received: from localhost.localdomain (shlinux2.ap.freescale.net [10.192.224.44]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id A7AB24024E; Fri, 5 Mar 2021 14:30:39 +0100 (CET) From: Dong Aisheng To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Cc: dongas86@gmail.com, kernel@pengutronix.de, shawnguo@kernel.org, robh+dt@kernel.org, linux-imx@nxp.com, jan.kiszka@siemens.com, Dong Aisheng , Mark Rutland , Fabio Estevam Subject: [PATCH v5 07/18] arm64: dts: imx8: add conn lpcg clocks Date: Fri, 5 Mar 2021 21:17:37 +0800 Message-Id: <1614950268-22073-9-git-send-email-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1614950268-22073-1-git-send-email-aisheng.dong@nxp.com> References: <1614950268-22073-1-git-send-email-aisheng.dong@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210305_133054_284477_9209DEE1 X-CRM114-Status: GOOD ( 10.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add conn lpcg clocks Cc: Rob Herring Cc: Mark Rutland Cc: devicetree@vger.kernel.org Cc: Shawn Guo Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Dong Aisheng --- ChangeLog: v3->v5: * no changes v2->v3: * update to use clock-indices property instead of bit-offset property v1->v2: * Use old SCU clock binding temporarily to avoid build warning due to SCU clock cell will be changed to 2. * add power domain propertyv1->v2: --- .../boot/dts/freescale/imx8-ss-conn.dtsi | 104 +++++++++++++++++- 1 file changed, 101 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 8691a43882fd..4220a5cdc249 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -4,15 +4,34 @@ * Dong Aisheng */ +#include +#include + conn_subsys: bus@5b000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - conn_lpcg: clock-controller@5b200000 { - reg = <0x5b200000 0xb0000>; - #clock-cells = <1>; + conn_axi_clk: clock-conn-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333333333>; + clock-output-names = "conn_axi_clk"; + }; + + conn_ahb_clk: clock-conn-ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <166666666>; + clock-output-names = "conn_ahb_clk"; + }; + + conn_ipg_clk: clock-conn-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <83333333>; + clock-output-names = "conn_ipg_clk"; }; usdhc1: mmc@5b010000 { @@ -83,4 +102,83 @@ fec2: ethernet@5b050000 { power-domains = <&pd IMX_SC_R_ENET_1>; status = "disabled"; }; + + /* LPCG clocks */ + conn_lpcg: clock-controller-legacy@5b200000 { + reg = <0x5b200000 0xb0000>; + #clock-cells = <1>; + }; + + sdhc0_lpcg: clock-controller@5b200000 { + reg = <0x5b200000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC0_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = , , + ; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; + }; + + sdhc1_lpcg: clock-controller@5b210000 { + reg = <0x5b210000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC1_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = , , + ; + clock-output-names = "sdhc1_lpcg_per_clk", + "sdhc1_lpcg_ipg_clk", + "sdhc1_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_1>; + }; + + sdhc2_lpcg: clock-controller@5b220000 { + reg = <0x5b220000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_SDHC2_CLK>, + <&conn_ipg_clk>, <&conn_axi_clk>; + clock-indices = , , + ; + clock-output-names = "sdhc2_lpcg_per_clk", + "sdhc2_lpcg_ipg_clk", + "sdhc2_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_2>; + }; + + enet0_lpcg: clock-controller@5b230000 { + reg = <0x5b230000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>, + <&clk IMX_CONN_ENET0_ROOT_CLK>, + <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + clock-indices = , , + , , + ; + clock-output-names = "enet0_ipg_root_clk", + "enet0_tx_clk", + "enet0_ahb_clk", + "enet0_ipg_clk", + "enet0_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_0>; + }; + + enet1_lpcg: clock-controller@5b240000 { + reg = <0x5b240000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>, + <&clk IMX_CONN_ENET1_ROOT_CLK>, + <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; + clock-indices = , , + , , + ; + clock-output-names = "enet1_ipg_root_clk", + "enet1_tx_clk", + "enet1_ahb_clk", + "enet1_ipg_clk", + "enet1_ipg_s_clk"; + power-domains = <&pd IMX_SC_R_ENET_1>; + }; };