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Mon, 12 Apr 2021 04:51:48 -0700 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Apr 2021 19:51:42 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 12 Apr 2021 19:51:41 +0800 From: Yongqiang Niu To: Chun-Kuang Hu CC: Rob Herring , Matthias Brugger , Philipp Zabel , "David Airlie" , Daniel Vetter , Jassi Brar , Yongqiang Niu , Fabien Parent , Dennis YC Hsieh , , , , , , , Hsin-Yi Wang Subject: [PATCH v4, 3/3] mailbox: cmdq: add mt8192 support Date: Mon, 12 Apr 2021 19:51:30 +0800 Message-ID: <1618228290-18413-4-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1618228290-18413-1-git-send-email-yongqiang.niu@mediatek.com> References: <1618228290-18413-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 447C2C1B621AAE91646F4EA40E3586078D4BF77CC13B96936FD04B446FFE24992000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210412_045153_827569_B306F42C X-CRM114-Status: GOOD ( 14.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org add mt8192 support Signed-off-by: Yongqiang Niu Signed-off-by: Hsin-Yi Wang --- drivers/mailbox/mtk-cmdq-mailbox.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c index e0d9a86..8da700a 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -36,6 +36,8 @@ #define CMDQ_THR_WAIT_TOKEN 0x30 #define CMDQ_THR_PRIORITY 0x40 +#define GCE_GCTL_VALUE 0x48 + #define CMDQ_THR_ACTIVE_SLOT_CYCLES 0x3200 #define CMDQ_THR_ENABLED 0x1 #define CMDQ_THR_DISABLED 0x0 @@ -77,11 +79,13 @@ struct cmdq { struct clk *clock; bool suspended; u8 shift_pa; + bool control_by_sw; }; struct gce_plat { u32 thread_nr; u8 shift; + bool control_by_sw; }; u8 cmdq_get_shift_pa(struct mbox_chan *chan) @@ -122,6 +126,8 @@ static void cmdq_init(struct cmdq *cmdq) int i; WARN_ON(clk_enable(cmdq->clock) < 0); + if (cmdq->control_by_sw) + writel(0x7, cmdq->base + GCE_GCTL_VALUE); writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i = 0; i <= CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); @@ -598,6 +604,7 @@ static int cmdq_probe(struct platform_device *pdev) cmdq->thread_nr = plat_data->thread_nr; cmdq->shift_pa = plat_data->shift; + cmdq->control_by_sw = plat_data->control_by_sw; cmdq->irq_mask = GENMASK(cmdq->thread_nr - 1, 0); err = devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, "mtk_cmdq", cmdq); @@ -663,11 +670,14 @@ static int cmdq_probe(struct platform_device *pdev) static const struct gce_plat gce_plat_v2 = {.thread_nr = 16}; static const struct gce_plat gce_plat_v3 = {.thread_nr = 24}; static const struct gce_plat gce_plat_v4 = {.thread_nr = 24, .shift = 3}; +static const struct gce_plat gce_plat_v5 = {.thread_nr = 24, .shift = 3, + .control_by_sw = true}; static const struct of_device_id cmdq_of_ids[] = { {.compatible = "mediatek,mt8173-gce", .data = (void *)&gce_plat_v2}, {.compatible = "mediatek,mt8183-gce", .data = (void *)&gce_plat_v3}, {.compatible = "mediatek,mt6779-gce", .data = (void *)&gce_plat_v4}, + {.compatible = "mediatek,mt8192-gce", .data = (void *)&gce_plat_v5}, {} };