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Thu, 2 Feb 2023 01:43:13 -0800 Received: from [172.23.64.3] (port=36999 helo=xhdvnc103.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1pNW7d-0003R6-0N; Thu, 02 Feb 2023 01:43:13 -0800 Received: by xhdvnc103.xilinx.com (Postfix, from userid 90444) id 554801055BD; Thu, 2 Feb 2023 15:12:24 +0530 (IST) From: Manikanta Guntupalli To: , , , , , , , , CC: , , , , , Raviteja Narayanam Subject: [PATCH V4 4/9] i2c: xiic: Add wait for FIFO empty in send_tx Date: Thu, 2 Feb 2023 15:11:33 +0530 Message-ID: <1675330898-563-5-git-send-email-manikanta.guntupalli@amd.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1675330898-563-1-git-send-email-manikanta.guntupalli@amd.com> References: <1675330898-563-1-git-send-email-manikanta.guntupalli@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1NAM02FT0043:EE_|MW4PR02MB7347:EE_ X-MS-Office365-Filtering-Correlation-Id: d0847ade-83cc-4a36-202b-08db0501e9a1 X-MS-Exchange-SenderADCheck: 0 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Feb 2023 09:43:17.5033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d0847ade-83cc-4a36-202b-08db0501e9a1 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0043.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR02MB7347 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230202_014320_766480_1921D8EC X-CRM114-Status: GOOD ( 10.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Raviteja Narayanam If the tx_half_empty interrupt comes first instead of tx_empty, STOP bit is generated even before all the bytes are transmitted out on the bus. STOP bit should be sent only after all the bytes in the FIFO are transmitted out of the FIFO. So wait until FIFO is empty before sending the STOP bit. Signed-off-by: Raviteja Narayanam Signed-off-by: Manikanta Guntupalli Acked-by: Michal Simek --- drivers/i2c/busses/i2c-xiic.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index edc64b79e293..57084696429c 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -436,6 +436,13 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) data |= XIIC_TX_DYN_STOP_MASK; } else { u8 cr; + int status; + + /* Wait till FIFO is empty so STOP is sent last */ + status = xiic_wait_tx_empty(i2c); + if (status) + return; + /* Write to CR to stop */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr &